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Memory Architecture Evaluation for Video Encoding on Enhanced Embedded Processors

  • Ali Iranpour
  • Krzysztof Kuchcinski
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)

Abstract

In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 19-22 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.

Keywords

Discrete Cosine Transform Cache Size Data Cache Memory Architecture Embed Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Chouliaras, V.A., et al.: A Multi-Standard Video Accelerator based on a Vector Architecture. IEEE Trans. Consum. Elec. 51(1) (February 2005)Google Scholar
  2. 2.
    Nunez, J.L., Chouliaras, V.A.: High-performance Arithmetic Coding VLSI Macro for the H264 Video Compression Standard. IEEE Trans. Consum. Elec. 51(1) (February 2005)Google Scholar
  3. 3.
    Huang, Y.-W., Hsieh, B.-Y., Chen, T.-C., Chen, L.-G.: Hardware Design for H.264/AVC Intra Frame Coder. In: Proc. of IEEE ISCAS 2004, vol. 2, pp. II-269–272 (2004)Google Scholar
  4. 4.
    Wang, R.G., Li, J.T., Huang, C.: Motion Compensation Memory Access Optimization Strategies for H.264/AVC Decoder. In: Proc. of IEEE ICASSP 2005, vol. 5, pp. 97–100 (2005)Google Scholar
  5. 5.
    Stevens, A.: Level 2 Cache for High-performance ARM Core-based SoC System, White-paper ARM (January 2004), http://www.arm.com/
  6. 6.
    Asaduzzaman, A., et al.: Cache Optimization for Mobile Devices Running Multimedia Applications. In: Proc. IEEE ISMSE 2004, pp. 499–506 (2004)Google Scholar
  7. 7.
    McKee, S.A., Fang, Z., Valero, M.: An MPEG-4 Performance Study for non-SIMD, General Purpose Architectures. In: Proc. of IEEE ISPASS 2003, pp. 49–57 (2003)Google Scholar
  8. 8.
    Owens, J.D., et al.: Media Processing Applications on the Imagine Stream Processor. In: Proc. of IEEE ICCD 2002, pp. 295–302 (2002)Google Scholar
  9. 9.
    MPEG-4: ISO/IEC JTCI/SC29/WG11, ISO/IEC 14469:2000-2: Information on technology-coding of audio-video objects–Part 2:Visual, ISO/IEC, Genf, Switzerland (December 2000)Google Scholar
  10. 10.
    H.264/AVCSoftwareCoordination, JM, http://iphome.hhi.de/suehring/tml/
  11. 11.
    Priddle, C.: H.264 video encoder optimization with focus on very low complexity algorithms. M.S. thesis, Uppsala University (April 2005)Google Scholar
  12. 12.
    Iranpour, A.R., Kuchcinski, K.: Evaluation of SIMD Architecture Enhancement in Embedded Processors for MPEG-4. In: Proc. IEEE DSD (September 2004)Google Scholar
  13. 13.
    Joint Video Team (JVT) of ISO/IEC MPEG, ITU-T VCEG Text of ISO/IEC 14496 10:2004 Advance Video Coding Standard (second edition), ISO/IEC JTC1/SC29/WGII/N6359, Munich, Germany (March 2004) Google Scholar
  14. 14.
    Lappalainen, V., et al.: Performance of H.26L Video Encoder on General-Purpose Processor. Kluwer Journal of VLSI Sig. Proc. 34(3), 239–249 (2003)CrossRefGoogle Scholar
  15. 15.
    Iranpour, A.R., Kuchcinski, K.: Analyses of Embedded Processors for Streaming Media Applications. In: CAECW-8 (February 2005)Google Scholar
  16. 16.
    Lappalainen, V., Hämäläinen, T.D., Liuha, P.: Overview of Research Efforts on Media ISA Extentions and Their Usage in Video Coding. IEEE Trans. Circuit and System for Video tech. 12(8) (August 2002)Google Scholar
  17. 17.
    Vassiliadis, S., Juurlink, B., Hakkennes, E.: Complex Streamed Instructions: Introduction and Initial Evaluation. In: Proc. 26th Euromicro Conference, vol. 1, pp. 400–408 (2000)Google Scholar
  18. 18.
    Austin, T., et al.: SimpleScalar: An infrastructure for computer system modeling. IEEE Computer 35(2), 59–67 (2002)Google Scholar
  19. 19.
    Brooks, D., Tiwari, V., Martonosi, M.: Wattch: A Framework for Architectural-Level Power Analysis and Optimizations. In: Proc. ISCA 2000, June 2000, pp. 83–94 (2000)Google Scholar
  20. 20.
  21. 21.
    Franchetti, F., Kral, S., Lorenz, J., Uberhuber, C.W.: Efficient Utilization of SIMD Extensions. IEEE Proceedings 93(2) (February 2005)Google Scholar
  22. 22.
    Tuau, J.-C., Chang, T.-S., Jen, C.-W.: On the Data Reuse and Memory Bandwidth Analysis for Full-Search Block-Matching VLSI Architecture. IEEE Trans. Circuit and Syst. For Video tech. 12(1) (January 2002)Google Scholar
  23. 23.
    Cho, C.-Y., Huang, S.-Y., Wang, J.-S.: An Embedded Merging Scheme for H.264/AVC Motion Estimation. In: Proc. of ICIP 2003, vol. 1, p. I-909 (2003)Google Scholar
  24. 24.
    Stolberg, H.J., et al.: HiBRID-SoC:A Multi-Core SoC Architecture for Multimedia Signal Processing. Journal VLSI Signal Processing System 41, 9–20 (2005)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Ali Iranpour
    • 1
  • Krzysztof Kuchcinski
    • 1
  1. 1.Department of Computer ScienceLund UniversityLundSweden

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