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SAD Prefetching for MPEG4 Using Flux Caches

  • Georgi N. Gaydadjiev
  • Stamatis Vassiliadis
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)

Abstract

In this paper, we consider flux caches prefetching and a media application. We analyze the MPEG4 encoder workload with realistic data set in a scenario representative for the embedded systems domain. Our study shows that different well known data prefetch mechanisms can gain little reduction in the cache miss ratios when applied on the complete MPEG4 application. Furthermore, we investigate the potential improvement when dedicated prefetching strategies are applied to the sum of absolute differences (SAD) kernels in MPEG4. We propose a flux cache mechanism that dynamically invokes cache designs with dedicated prefetching engines that can fully utilize the available memory bandwidth. We show that our proposal improves the cache miss ratios by a factor close to 3x.

Keywords

Flux caches Prefetching mechanisms Reconfigurable architectures Multimedia 

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References

  1. 1.
    Gaydadjiev, G.N., Vassiliadis, S.: Flux caches: What are they and are they useful? In: Hämäläinen, T.D., Pimentel, A.D., Takala, J., Vassiliadis, S. (eds.) SAMOS 2005. LNCS, vol. 3553, pp. 93–102. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  2. 2.
    VanderWiel, S.P., Lilja, D.J.: Data prefetch mechanisms. ACM Computing Surveys 32, 174–199 (2000)CrossRefGoogle Scholar
  3. 3.
    Smith, A.J.: Sequential program prefetching in memory hierarchies. IEEE Computer 11 12, 7–21 (1978)Google Scholar
  4. 4.
    Vassiliadis, S., Wong, S., Gaydadjiev, G.N., Bertels, K., Kuzmanov, G.K., Panainte, E.M.: The molen polymorphic processor. IEEE Transactions on Computers, 1363–1375 (2004)Google Scholar
  5. 5.
    Lin, W.F., Reinhardt, S.K., Burger, D.: Reducing DRAM latencies with an integrated memory hierarchy design. In: HPCA, pp. 301–312 (2001)Google Scholar
  6. 6.
    Gornish, E.H., Veidenbaum, A.: An integrated hardware/software data prefetching scheme for shared-memory multiprocessors. Int. J. Parallel Program 27, 35–70 (1999)CrossRefGoogle Scholar
  7. 7.
    Chen, T.F.: An effective programmable prefetch engine for on-chip caches. In: MICRO 28: Proceedings of the 28th annual international symposium on Microarchitecture, pp. 237–242. IEEE Computer Society Press, Los Alamitos (1995)CrossRefGoogle Scholar
  8. 8.
    Zhang, Z., Torrellas, J.: Speeding up irregular applications in shared-memory multiprocessors: memory binding and group prefetching. In: ISCA 1995: Proceedings of the 22nd annual international symposium on Computer architecture, pp. 188–199. ACM Press, New York (1995)Google Scholar
  9. 9.
    Wang, Z., Burger, D., McKinley, K.S., Reinhardt, S.K., Weems, C.C.: Guided region prefetching: a cooperative hardware/software approach. In: ISCA 2003: Proceedings of the 30th annual international symposium on Computer architecture, pp. 388–398. ACM Press, New York (2003)Google Scholar
  10. 10.
    Corbal, J., Espasa, R., Valero, M.: Three-dimensional memory vectorization for high bandwidth media memory systems. In: MICRO 35: Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, pp. 149–160. IEEE Computer Society Press, Los Alamitos (2002)Google Scholar
  11. 11.
    Kuzmanov, G., Gaydadjiev, G.N., Vassiliadis, S.: Visual data rectangular memory. In: Danelutto, M., Vanneschi, M., Laforenza, D. (eds.) Euro-Par 2004. LNCS, vol. 3149, pp. 760–767. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  12. 12.
    Edler, J., Hill, M.D.: Dinero IV trace-driven uniprocessor cache simulator (1998), http://www.cs.wisc.edu/~markhill/DineroIV
  13. 13.
    Smith, A.J.: Cache Memories. Computing Surveys 14, 473–530 (1982)CrossRefGoogle Scholar
  14. 14.
    Burger, D., Austin, T.M., Bennett, S.: Evaluating future microprocessors: The simplescalar tool set. Technical Report CS-TR-1996-1308 (1996)Google Scholar
  15. 15.
  16. 16.
  17. 17.
  18. 18.
    Vassiliadis, S., Gaydadjiev, G.N., Bertels, K., Panainte, E.M.: The molen programming paradigm. In: Proceedings of the Third International Workshop on Systems, Architectures, Modeling, and Simulation, pp. 1–10 (2003)Google Scholar
  19. 19.
    Panainte, E.M., Bertels, K., Vassiliadis, S.: Compiling for the molen programming paradigm. In: Y. K. Cheung, P., Constantinides, G.A. (eds.) FPL 2003. LNCS, vol. 2778, pp. 900–910. Springer, Heidelberg (2003)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Georgi N. Gaydadjiev
    • 1
  • Stamatis Vassiliadis
    • 1
  1. 1.Computer Engineering Laboratory, Electrical Engineering, Mathematics and Computer Science Dept., EEMCSTU DelftThe Netherlands

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