Abstract
Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Weste, N., Eshraghian, K.: Principles of CMOS VLSI Design: A Systems Perspective. Addison-Wesley, Reading (1985)
Chandrakasan, A., Sheng, S., Brodersen, R.: Low-power CMOS digital design. IEEE Journal of Solid State Circuits 27, 473–483 (1992)
Reeves, K., Sienski, K., Field, C.: Reconfigurable hardware accelerator for embedded DSP. In: Schewel, J., Athanas, P.M., Bove, V.M., Watson, J. (eds.) Proc. SPIE High-Speed Comp. Dig. Sig. Proc. Filtering Using Reconf. Logic, Boston, MA, vol. 2914, pp. 332–340 (1996)
Chang, A., Dally, W.: Explaining the gap between ASIC and custom power: A custom perspective. In: Proc. IEEE DAC, Anaheim, CA, pp. 281–284 (2005)
Baas, B.M.: A low-power, high-performance, 1024-point FFT processor. IEEE Solid State Circuits 43, 380–387 (1999)
Zhao, Y., Erdogan, A., Arslan, T.: A low-power and domain-specific reconfigurable fft fabric for system-on-chip applications. In: Proc. 19th IEEE Parallel and Distrubuted Prosessing Symp. Reconf. Logic, Denver, CO (2005)
Lin, Y.T., Tsai, P.Y., Chiueh, T.D.: Low-power variable-length fast fourier transform processor. In: Proc. IEE Computers and Digital Techniques, vol. 152, pp. 499–506 (2005)
Wang, A., Chandrakasan, A.: A 180-mV subthreshold FFT processor using a minimum energy design methodology. IEEE J. Solid State Circuits 40, 310–319 (2005)
Granata, J., Conner, M., Tolimieri, R.: Recursive fast algorithms and the role of the tensor product. IEEE Trans. Signal Processing 40, 2921–2930 (1992)
Corporaal, H.: Microprocessor Architectures: From VLIW to TTA. John Wiley & Sons, Chichester (1997)
Mäkinen, R.: Fast Fourier transform on transport triggered architectures. Master’s thesis, Tampere Univ. Tech., Tampere, Finland (2005)
Wanhammar, L.: DSP Integrated Circuits. Academic Press, San Diego (1999)
Lefurgy, C., Mudge, T.: Code compression for DSP. Technical Report CSE-TR-380-98, EECS Department, University of Michigan (1998)
Corporaal, H., Arnold, M.: Using transport triggered architectures for embedded processor design. Integrated Computer-Aided Eng. 5, 19–38 (1998)
Intel: StrongARM SA-110 Microprocessor for Portable Applications Brief Datasheet (1999)
Lim, S., Crosland, A.: Implementing FFT in an FPGA co-processor. In: The International Embedded Solutions Event (GPSx), Santa Clara, CA, pp. 230–233 (2004)
Agarwala, S., Anderson, T., Hill, A., Ales, M., Damodaran, R., Wiley, P., Mullinnix, S., Leach, J., Lell, A., Gill, M., Rajagopal, A., Chachad, A., Agarwala, M., Apostol, J., Krishnan, M., Duc-Bui, Quang-An, Nagaraj, N., Wolf, T., Elappuparackal, T.: A 600 MHz VLIW DSP. IEEE J. Solid State Circuits 37, 1532–1544 (2002)
Rixner, S., Dally, W., Kapasi, U., Khailany, B., Lopez-Lagunas, A., Mattson, P., Owens, J.: A bandwidth-efficient architecture for media processing. In: Proc. Annual ACM/IEEE Int. Symp. Microarchitecture, Dallas, TX, pp. 3–13 (1998)
Texas Instruments, Inc. Dallas, TX: TMS320C64x DSP Library Programmer’s Reference (2003)
Deleganes, M., Douglas, J., Kommandur, B., Patyra, M.: Designing a 3 GHz, 130 nm, Intel® Pentium ®4 processor. Digest of Technical Papers Symp. VLSI Circuits, Honolulu, HI, pp. 230–233 (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2006 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Pitkänen, T., Mäkinen, R., Heikkinen, J., Partanen, T., Takala, J. (2006). Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform. In: Vassiliadis, S., Wong, S., Hämäläinen, T.D. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2006. Lecture Notes in Computer Science, vol 4017. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11796435_24
Download citation
DOI: https://doi.org/10.1007/11796435_24
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-36410-8
Online ISBN: 978-3-540-36411-5
eBook Packages: Computer ScienceComputer Science (R0)