Low-Power, High-Performance TTA Processor for 1024-Point Fast Fourier Transform

  • Teemu Pitkänen
  • Risto Mäkinen
  • Jari Heikkinen
  • Tero Partanen
  • Jarmo Takala
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)


Transport Triggered Architecture (TTA) offers a cost-effective trade-off between the size and performance of ASICs and the programmability of general-purpose processors. This paper presents a study where a high performance, low power TTA processor was customized for a 1024-point complex-valued fast Fourier transform (FFT). The proposed processor consumes only 1.55 μJ of energy for a 1024-point FFT. Compared to other reported FFT implementations with reasonable performance, the proposed design shows a significant improvement in energy-efficiency.


Fast Fourier Transform Field Programmable Gate Array Very Long Instruction Word Twiddle Factor Code Compression 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Teemu Pitkänen
    • 1
  • Risto Mäkinen
    • 1
  • Jari Heikkinen
    • 1
  • Tero Partanen
    • 1
  • Jarmo Takala
    • 1
  1. 1.Tampere University of TechnologyTampereFinland

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