Efficient Automated Clock Gating Using CoDeL

  • Nainesh Agarwal
  • Nikitas J. Dimopoulos
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4017)


We present a highly efficient automated clock gating platform for rapidly developing power efficient hardware architectures. Our language, called CoDeL, allows hardware description at the algorithm level, and thus dramatically reduces design time. We have extended CoDeL to automatically insert clock gating at the behavioral level to reduce dynamic power dissipation in the resulting architecture. This is, to our knowledge, the first hardware design environment that allows an algorithmic description of a component and yet produces a power aware design. To estimate the power savings, we have developed an estimation framework, which is shown to be consistent with the power savings obtained using statistical power analysis using Synopsys tools. To evaluate our platform we use the CoDeL implementation of a counter and various integer transforms used in the realm of DSP (Digital Signal Processing): discrete wavelet transform, discrete cosine transform and an integer transform used in the H.264 (MPEG4 Part 10) video compression standard. These designs are then clock gated using CoDeL and Synopsys. A simulation based power analysis on the designed circuits shows that CoDeL’s clock gating performs better than Synopsys’ automated clock gating. CoDeL reduces the power dissipation by 83% on average, while Synopsys gives 81% savings.


Discrete Cosine Transform Power Saving Switching Activity Combinational Logic Lift Scheme 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Nainesh Agarwal
    • 1
  • Nikitas J. Dimopoulos
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of VictoriaVictoriaCanada

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