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Neural Network Implementation in Reprogrammable FPGA Devices – An Example for MLP

  • Marek Gorgoń
  • Mateusz Wrzesiński
Part of the Lecture Notes in Computer Science book series (LNCS, volume 4029)

Abstract

In the present paper an implementation of multilayer perceptron (MLP) in a new generation SRAM-FPGA device is discussed. The presented solution enables easy realization of MLP with arbitrary structure and calculation accuracy. The solution is based on utilization of the structural parallelism of the FPGA device and economical realization of individual neurons. A flexible and effective method has been applied for approximation of the nonlinear activation function by a series of linear segments. Selection mechanisms have been also introduced for a compromise between the amount of logical resources used and the network operation speed. Therefore the presented solution can be applied both for implementation of big networks in small FPGA devices and for implementation working in real time, for which high operation speed is required.

Keywords

Activation Function Synaptic Function Activation Block Hardware Resource Logical Resource 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Marek Gorgoń
    • 1
  • Mateusz Wrzesiński
    • 1
  1. 1.Department of AutomaticsAGH University of Science and Technology, Biocybernetic LaboratoryKrakówPoland

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