Fully-Pipelining Hardware Implementation of Neural Network for Text-Based Images Retrieval
Many hardware implementations cannot execute the software MLPs’ applications using weight of floating-point data, because hardware design of MLPs usually uses fixed-point arithmetic for high speed and small area. The hardware design using fixed-point arithmetic has two important drawbacks which are low accuracy and flexibility. Therefore, we propose a fully-pipelining architecture of MLPs using floating-point arithmetic in order to solve these two problems. Thus our design method can implement the MLPs having the processing speed improved by optimizing the number of hidden nodes in a repeated processing. We apply a software application of MLPs-based text detection that is computed to be 1722120 times for text detection of a 1152×1546 sized image to hardware implementation. Our preliminary result shows a performance enhancement of about eleven times faster using a fully-pipelining architecture than the software application.
KeywordsHide Layer Output Layer Hide Node Sigmoid Function Hardware Implementation
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