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Implementation of a Neural Network Processor Based on RISC Architecture for Various Signal Processing Applications

  • Dong-Sun Kim
  • Hyun-Sik Kim
  • Duck-Jin Chung
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3973)

Abstract

In this paper, hybrid neural network processor (HANNP) is designed in VLSI. The HANNP has RISC based architecture leading to an effective general digital signal processing and artificial neural networks computation. The architecture of a HANNP including the general digital processing units such as 64-bit floating-point arithmetic unit (FPU), a control unit (CU) and neural network processing units such as artificial neural computing unit (NNPU), specialized neural data bus and interface unit, etc. The HANNP is modeled in Veilog HDL and implemented with FPGA. Character recognition problems and Kohonen self-organization problems are applied to the proposed HANNP to justify its applicability to real engineering problems.

Keywords

Synaptic Weight Arithmetic Group Arithmetic Unit Complex Problem Solv Arithmetic Logical Unit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Dong-Sun Kim
    • 1
  • Hyun-Sik Kim
    • 1
  • Duck-Jin Chung
    • 2
  1. 1.DxB · Communication Convergence Research CenterKorea Electronics Technology InstituteGyeonggi-doKorea
  2. 2.Information Technology and TelecommunicationsInha UniversityIncheonKorea

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