Implementation of a Neural Network Processor Based on RISC Architecture for Various Signal Processing Applications
In this paper, hybrid neural network processor (HANNP) is designed in VLSI. The HANNP has RISC based architecture leading to an effective general digital signal processing and artificial neural networks computation. The architecture of a HANNP including the general digital processing units such as 64-bit floating-point arithmetic unit (FPU), a control unit (CU) and neural network processing units such as artificial neural computing unit (NNPU), specialized neural data bus and interface unit, etc. The HANNP is modeled in Veilog HDL and implemented with FPGA. Character recognition problems and Kohonen self-organization problems are applied to the proposed HANNP to justify its applicability to real engineering problems.
KeywordsSynaptic Weight Arithmetic Group Arithmetic Unit Complex Problem Solv Arithmetic Logical Unit
Unable to display preview. Download preview PDF.
- 1.Shiva, S.G. (ed.): Pipelined and Parallel Computer Architectures. Harper-Collins, New York (1996)Google Scholar
- 2.Boulet, P., Fortes, J.A.B.: Experimental Evaluation of Affine Schedules for Matrix Multiplication on the MasPar Architecture. In: Proc. lst International Conf. on Massively Parallel Computing Systems, pp. 452–459 (1994)Google Scholar
- 3.Lam, K.D., Pattnaik, V., Seung-Moon, Y., Torrellas, J., Huang, W., Kang, Y., Zhenzhou, G.: FlexRAM: Toward an Advanced Intelligent Memory System. In: Proceedings of International Conf. on Computer Design 1999, pp. 192–201 (1999)Google Scholar
- 4.Chong, F., Oskin, M., Sherwood, T.: Active pages: A Computation Model for Intelhgent Memory. In: Proc. 25th Annual International Symposium on Computer Architecture, pp. 192–203 (1998)Google Scholar