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Design and Implementation of FPGA Based High-Performance Intrusion Detection System

  • Byoung-Koo Kim
  • Young-Jun Heo
  • Jin-Tae Oh
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3975)

Abstract

As network technology presses forward, Gigabit Ethernet has become the actual standard for large network installations. Therefore, it is necessary to research on security analysis mechanism, which is capable to process high traffic volume over the high-speed network. This paper proposes FPGA based high-performance IDS to detect and respond variant attacks on high-speed links. Most of all, It is possible through the pattern matching function and heuristic analysis function that is processed in FPGA Logic. In other words, we focus on the network intrusion detection mechanism applied in high-speed network.

Keywords

Field Programmable Gate Array Intrusion Detection Traffic Volume Incoming Packet High Traffic Volume 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Kruegel, C., Valeur, F., Vigna, G., Kemmerer, R.: Stateful intrusion detection for high-speed networks. In: Proceedings of the IEEE Symposium on Security and Privacy, pp. 266–274 (2002)Google Scholar
  2. 2.
    Roesch, M.: Snort-Lightweight Intrusion Detection for Networks. In: Proceedings of the USENIX LISA 1999 Conference (November 1999)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Byoung-Koo Kim
    • 1
  • Young-Jun Heo
    • 1
  • Jin-Tae Oh
    • 1
  1. 1.Security Gateway System TeamElectronics and Telecommunications Research InstituteDaejeonKorea

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