Optimized Design of Interconnected Bus on Chip for Low Power

  • Donghai Li
  • Guangsheng Ma
  • Gang Feng
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3994)


In this paper, we firstly propose an on-chip bus power consumption model, which includes the self transition power dissipated on the signal lines and the coupled transition power dissipated between every two signal lines. And then a new heuristic algorithm is proposed to determine a physical order of signal lines in bus. Experimental results show an average power saving 26.85%.


Heuristic Algorithm Transition Activity Couple Transition Signal Line Very Large Scale Integrate 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Donghai Li
    • 1
  • Guangsheng Ma
    • 1
  • Gang Feng
    • 1
  1. 1.College of Computer Science & TechnologyHaerbin Engineering UniversityHaerbinChina

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