Speedup Requirements for Output Queuing Emulation with a Sliding-Window Parallel Packet Switch

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3994)


This investigation uses an approximate Markov chain to determine whether a sliding window (SW) parallel packet switch (PPS), only operating more slowly than the external line speed, can emulate a first-come first-served (FCFS) output-queued (OQ) packet switch. A new SW packet switching scheme for PPS, which is called SW-PPS, was presented in the authors’ earlier study [1]. The PPS class is characterized by deployment of distributed center-stage switch planes with memory buffers that run slower than the external line speed. Given identical Bernoulli and Bursty data traffic, the proposed SW-PPS provided substantially outperformed typical PPS, in which the dispatch algorithm applies a round-robin method (RR) [1]. This study develops a presented Markov chain model that successfully exhibits throughput, cell delay and cell drop rate. A simulation reveals that the chains are accurate for reasonable network loads. Major findings concerning the presented model are that: (1) the throughput and cell drop rates of a SW-PPS can theoretically emulate those of aFCFS-OQ packet switch when each slower packet switch operates at a rate of around R/K (Eq. 19); and, (2) this investigation also proves the theoretical possibility that the cell delay of a SW-PPS can emulate that of an FCFS-OQ packet switch, when each slower packet switch operates at a rate of about (R/cell delay of FCFS-OQ switch) (Eq. 20).


Output Port Memory Location Memory Space Markov Chain Model Queue Size 
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  1. 1.
    Liu, C.L., Lin, W.: Performance Analysis of the Sliding-Window Parallel Packet Switch. In: IEEE 40th International Conference on Communications, ICC 2005, vol. 1, pp. 179–183 (2005)Google Scholar
  2. 2.
    Iyer, S.: Analysis of the Parallel Packet Switch Architecture. IEEE Transactions on Networking 11(2), 314–324 (2003)CrossRefMathSciNetGoogle Scholar
  3. 3.
    Aslam, A., Christensen, K.: Parallel packet switching using multiplexers with virtual input queues. In: LCN 2002, pp. 270–277 (2002)Google Scholar
  4. 4.
    Szymanski, T., Shaikh, S.: Markov chain analysis of packet-switched banyans with arbitrary switch sizes, queue sizes, link multiplicities and speedups. In: Infocom 1989, vol. 3, pp. 960–971 (1989)Google Scholar
  5. 5.
    Karol, M., Hluchyj, M., Morgan, S.: Input Versus Output Queueing on a Space-Division Packet Switch. IEEE Transactions on Communications 35(12), 1347–1356 (1987)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  1. 1.Department of Computer ScienceNational Chung-Hsing UniversityTaichungTaiwan
  2. 2.Nan Kai Institute of Technology 

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