Compile-Time Energy Optimization for Parallel Applications in On-Chip Multiprocessors

  • Juan Chen
  • Huizhan Yi
  • Xuejun Yang
  • Liang Qian
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3992)


Energy consumption is becoming one of the key optimization objects in on-chip multiprocessor. Minimizing the energy consumption without parallel performance loss is concerned. In this paper, we focus on a DVFS-enabled on-chip multiprocessor architecture, which allows dynamically adjusting each processor’s voltage/frequency or shut down unused processors so to obtain energy savings. A detailed analytical model is provided and validated by experiments. Experimental results show energy saving can be up to 10.34% without performance loss.


Energy Saving Sparse Matrix Performance Loss Energy Optimization Parallel Application 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Juan Chen
    • 1
  • Huizhan Yi
    • 1
  • Xuejun Yang
    • 1
  • Liang Qian
    • 2
  1. 1.School of ComputerNational University of Defense TechnologyChangshaP.R.China
  2. 2.Interdisciplinary Research Centre in MaterialsUniversity of BirminghamUK

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