Low Complexity Systolic Architecture for Modular Multiplication over GF(2m)

  • Hyun-Sung Kim
  • Sung-Woon Lee
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3991)


The modular multiplication is known as an efficient basic operation for public key cryptosystems over GF(2 m ). Various systolic architectures for performing the modular multiplication have already been proposed based on a standard basis representation. However, they have high hardware complexity and long latency. Thereby, this paper presents a new algorithm and architecture for the modular multiplication in GF(2 m ). First, a new algorithm is proposed based on the LSB-first scheme using a standard basis representation. Then, bit serial systolic multiplier is derived with a low hardware complexity and small latency. Since the proposed architecture incorporates simplicity, regularity, and modularity, it is well suited to VLSI implementation and can be easily applied to modular exponentiation architecture. Furthermore, the architecture will be utilized for the basic architecture of crypto-processor.


Systolic Array Hardware Complexity Modular Multiplication VLSI Implementation Primitive Polynomial 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Hyun-Sung Kim
    • 1
  • Sung-Woon Lee
    • 2
  1. 1.School of Computer EngineeringKyungil UniversityKyungsansiKorea
  2. 2.Dept. of Information SecurityTongmyong UniversityBusanKorea

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