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SAT-Based Verification Methods and Applications in Hardware Verification

  • Aarti Gupta
  • Malay K. Ganai
  • Chao Wang
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3965)

Abstract

Verification methods based on Boolean Satisfiability (SAT) have emerged as a promising alternative to BDD-based symbolic model checking methods. This paper provides a tutorial on various SAT-based verification methods we have developed for verifying large hardware designs. We focus separately on methods for finding bugs and for finding proofs for correctness properties, along with highlighting the many common themes that benefit these methods. We also describe practical experiences with these methods implemented in our verification platform called VeriSol (formerly DiVer), which has been used successfully in industry practice.

Keywords

Model Check Conjunctive Normal Form Symbolic Model Check Bound Model Check Conjunctive Normal Form Formula 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Aarti Gupta
    • 1
  • Malay K. Ganai
    • 1
  • Chao Wang
    • 1
  1. 1.NEC Laboratories AmericaPrincetonUSA

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