Hardware Design and Simulation for Verification

  • Nicola Bombieri
  • Franco Fummi
  • Graziano Pravadelli
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3965)


The development of more and more complex embedded systems constitutes a very challenging task for EDA experts, due to their HW/SW-mixed nature joint to the high demand for quality and reliability. Recently, both industrial engineers and academic researchers have developed a very large number of techniques for dynamic verification in terms of co-simulation, which, in particular, address the different nature of hardware and software components of an embedded system. However, a widely accepted methodology does not exist. Thus, this paper is intended to provide a general view on simulation-based modeling and verification strategies for developing embedded systems. In particular, the paper is focussed on describing state-of-the art co-simulation approaches and verification strategies based on fault simulation and assertion checking.


Test Vector Fault Coverage Property Coverage Fault Simulation Register Transfer Level 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Nicola Bombieri
    • 1
  • Franco Fummi
    • 1
  • Graziano Pravadelli
    • 1
  1. 1.Università di VeronaVeronaItaly

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