An Efficient Hardware Implementation for AI Applications
A hardware architecture is presented, which accelerates the per- formance of intelligent applications that are based on logic programming. The logic programs are mapped on hardware and more precisely on FPGAs (Field Programmable Gate Array). Since logic programs may easily be transformed into an equivalent Attribute Grammar (AG), the underlying model of implementing an embedded system for the aforementioned applications can be that of an AG evaluator. Previous attempts to the same problem were based on the use of two separate components. An FPGA was used for mapping the inference engine and a conventional RISC microprocessor for mapping the unification mechanism and user defined additional semantics. In this paper a new architecture is presented, in order to drastically reduce the number of the required processing elements by a factor of n (length of input string). This fact and the fact of using, for the inference engine, an extension of the most efficient parsing algorithm, allowed us to use only one component i.e. a single FPGA board, eliminating the need for an additional external RISC microprocessor, since we have embedded two “PicoBlaze” Soft Processors into the FPGA. The proposed architecture is suitable for embedded system applications where low cost, portability and low power consumption is of crucial importance. Our approach was tested with numerous examples in order to establish the performance improvement over previous attempts.
KeywordsLogic Program Field Programmable Gate Array Logic Programming Inference Engine Attribute Evaluation
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- 4.Papakonstantinou, G., Kontos, J.: Knowledge Representation with Attribute Grammars. The Computer Journal 29(3) (1986)Google Scholar
- 5.Papakonstantinou, G., Moraitis, C., Panayiotopoulos, T.: An attribute grammar interpreter as a knowledge engineering tool. Applied Informatics 9/86, 382–388 (1986)Google Scholar
- 6.Clocksin, W.F., Mellish, C.S.: Programming in PROLOGGoogle Scholar
- 7.Panagopoulos, I., Pavlatos, C., Papakonstantinou, G.: An Embedded System for Artificial Intelligence Applications. International Journal of Computational Intelligence (2004)Google Scholar
- 8.Panagopoulos, I., Pavlatos, C., Papakonstantinou, G.: An Embedded Microprocessor for Intelligence Control. Journal of Rob. and Intel. SystemsGoogle Scholar
- 10.Chen, H., Chen, X.: Shape recognition using VLSI Architecture. The International Journal of Pattern Recognition and Artificial Intelligence (1993)Google Scholar
- 12.Demers, A., Reps, T., Teitelbaum, T.: Incremental evaluation for attribute grammars with application to syntax-directed editors. In: Conf. Rec. 8th Annu. ACM symp. Principles Programming Languages, January 1981, pp. 415–418 (1981)Google Scholar
- 13.Pavlatos, C., Panagopoulos, I., Papakonstantinou, G.: A programmable Pipelined Coprocessor for Parsing Applications. In: Workshop on Application Specific Processors (WASP) CODES, Stockholm (September 2004)Google Scholar
- 14.Chiang, Y., Fu, K.: Parallel parsing algorithms and VLSI implementation for syntactic pattern recognition. IEEE Trans. on Pattern Analysis and Machine Intelligence PAMI-6 (1984)Google Scholar
- 15.Pavlatos, C., Dimopoulos, A., Papakonstantinou, G.: An Intelligent Embedded System for Control Applications. In: Workshop on Modeling and Control of Complex Systems, Cyprus (2005)Google Scholar
- 17.Floyd, R.: The Syntax of Programming Languages-A Survey. IEEE Transactions on Electr. Comp. EC 13(4) (1964)Google Scholar