FPGA Implementation of the Conjugate Gradient Method

  • Oleg Maslennikow
  • Volodymyr Lepekha
  • Anatoli Sergyienko
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3911)


The rational fraction number system is proposed to solve the algebraic problems in FPGA devices. The fraction number consists of the n-bit integer numerator and the n -bit integer denominator, and can represent numbers with 2n bit mantissa. Experimental linear equation system solver was developed in FPGA device, which implements the recursive conjugate gradient method. Its hardware arithmetic unit can calculate addition, multiplication, and division of fraction numbers with n=35 in a pipelined mode. The proposed unit operates with the band matrices with the dimensions up to 3500.


Rational Fraction Digital Signal Processing Field Programmable Gate Array Conjugate Gradient Method Arithmetic Unit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Oleg Maslennikow
    • 1
  • Volodymyr Lepekha
    • 2
  • Anatoli Sergyienko
    • 2
  1. 1.Technical University of KoszalinKoszalinPoland
  2. 2.National Technical University of UkraineKievUkraine

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