Taking Advantage of the SHECS-Based Critical Sections in the Shared Memory Parallel Architectures

  • Tomasz Madajczak
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3911)


This document presents a new method for implementing critical sections in the shared memory parallel architectures such as multithreaded multiprocessors integrated on a die. The method bases on Shared Explicit Cache System (SHECS) implemented in the multiprocessor. The document presents the concept of system architecture equipped with SHECS, the algorithm to implement operating system or application level locking service, and the results obtained with the method simulation on the network processor Intel IXP2800.


Critical Section Cache Coherence FIFO Queue Network Processor Cache System 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Tomasz Madajczak
    • 1
    • 2
  1. 1.Faculty of Electronic, Telecommunication and Informatics, Dep. of Computer Systems ArchitecturesGdansk University of TechnologyGdanskPoland
  2. 2.Intel Technology Poland Sp. z o.o. ul.GdanskPoland

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