Model Driven Scheduling Framework for Multiprocessor SoC Design

  • Ashish Meena
  • Pierre Boulet
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3911)


The evolution of technologies is enabling the integration of complex platforms in a single chip, called a System-on-Chip (SoC). Modern SoCs may include several CPU subsystems to execute software and sophisticated interconnect in addition to specific hardware subsystems.

Designing such mixed hardware and software systems requires new methodologies and tools or to enhance old tools. These design tools must be able to satisfy many relative trade-offs (real-time, performance, low power consumption, time to market, re-usability, cost, area, etc).

It is recognized that the decisions taken for scheduling and mapping at a high level of abstraction have a major impact on the global design flow. They can help in satisfying different trade-offs before proceeding to lower level refinements.

To provide good potential to scheduling and mapping decisions we propose in this paper a static scheduling framework for MpSoC design. We will show why it is necessary to and how to integrate different scheduling techniques in such a framework in order to compare and to combine them. This framework is integrated in a model driven approach in order to keep it open and extensible.


Mapping Algorithm Mapping Heuristic Model Drive Engineering Task Parallelism Model Drive Engineering 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Amnell, T., Fersman, E., Mokrushin, L., Pettersson, P., Yi, W.: TIMES: a tool for schedulability analysis and code generation of real-time systems. In: Larsen, K.G., Niebert, P. (eds.) FORMATS 2003. LNCS, vol. 2791, Springer, Heidelberg (2004)CrossRefGoogle Scholar
  2. 2.
    Andrew, J.: Framework for task scheduling in heterogeneous distributed computing using genetic algorithms. In: 15th Artificial Intelligence and Cognitive Science Conference, Castlebar, Mayo, Ireland (2004)Google Scholar
  3. 3.
    Benini, L., Micheli, G.D.: Networks on chips: A new SoC paradigm. Computer 35(1), 70–78 (2002)CrossRefGoogle Scholar
  4. 4.
    Boulet, P., Dekeyser, J.-L., Dumoulin, C., Marquet, P.: MDA for System-on-Chip design, intensive signal processing experiment. In: FDL 2003, Fankfurt, Germany (September 2003)Google Scholar
  5. 5.
    Boulet, P., Meena, A.: The case for globally irregular locally regular algorithm architecture adequation. In: Journées Francophones sur l’Adéquation Algorithme Architecture (JFAAA 2005), Dijon, France (January 2005)Google Scholar
  6. 6.
    Buyya, R., Murshed, M.: GridSim: A toolkit for the modeling and simulation of distributed resource management and scheduling for grid computing. In: The Journal of Concurrency and Computation: Practice and Experience (CCPE), vol. 14, pp. 13–15. Wiley Press, Chichester (2002)Google Scholar
  7. 7.
    Casanova, H.: Simgrid: A toolkit for the simulation of application scheduling. In: CCGRID 2001. Proceedings of the 1st International Symposium on Cluster Computing and the Grid, Washington, DC, USA, 2001, p. 430. IEEE Computer Society, Los Alamitos (2001)Google Scholar
  8. 8.
    Chin, J., Nourani, M.: SoC test scheduling with power-time tradeoff and hot spot avoidance. In: DATE, pp. 710–711 (2004)Google Scholar
  9. 9.
    Cuccuru, A., Marquet, P., Dekeyser, J.-L.: Uml 2 as an adl: Hierarchichal hardware modeling. In: WADL 2004, Toulouse, France (August 2004)Google Scholar
  10. 10.
    Dumoulin, C., Boulet, P., Dekeyser, J.-L., Marquet, P.: UML 2.0 structure diagram for intensive signal processing application specification. Research Report RR-4766, INRIA (March 2003)Google Scholar
  11. 11.
    Gaspard2: Graphical array specification for parallel and distributed computing,
  12. 12.
    Jonsson, J., Vasell, J.: Evaluation and comparison of task allocation and scheduling methods for distributed real-time systems. In: ICECCS, pp. 226–229 (1996)Google Scholar
  13. 13.
    Liu, J.W.S., Redondo, J.-L., Deng, Z., Tia, T.-S., Bettati, R., Silberman, A., Storch, M., Ha, R., Shih, W.-K.: PERTS: A prototyping environment for real-time systems. Technical Report UIUCDCS-R-93-1802, University of Illinois at Urbana-Champaign (1993)Google Scholar
  14. 14.
    Luo, J., Jha, N.K.: Battery-aware static scheduling for distributed real-time embedded systems. In: DAC 2001. Proceedings of the 38th conference on Design automation, pp. 444–449. ACM Press, New York (2001)Google Scholar
  15. 15.
    Pasaje, J.L.M., Harbour, M.G., Drake, J.M.: MAST real-time view: A graphic UML tool for modeling object-oriented real-time systems (March 2001)Google Scholar
  16. 16.
    Stankovic, J.A., Zhu, R., Poornalingam, R., Lu, C., Yu, Z., Humphrey, M.: VEST: An aspect-based composition tool for real-time systems. In: The 9th IEEE Real-Time and Embedded Technology and Applications Symposium, Toronto, Canada (May 2003)Google Scholar
  17. 17.
    Su, C.-P., Wu, C.-W.: A graph-based approach to power-constrained SOC test scheduling. J. Electron. Test 20(1), 45–60 (2004)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Ashish Meena
    • 1
  • Pierre Boulet
    • 1
  1. 1.Laboratoire d’Informatique Fondamentale de LilleVilleneuve d’AscqFrance

Personalised recommendations