Low Power Microprocessor Design for Embedded Systems

  • Seong-Won Lee
  • Neungsoo Park
  • Jean-Luc Gaudiot
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3983)


Continuing advances in VLSI technology render a billion-transistor SOC device inevitable in the near future. However, along with this opportunity the excessive amount of power that billions of transistors will consume will be the most important challenge to the design of the future chips. Many techniques have been developed in order to reduce the power consumption of microprocessors. Unfortunately, this often comes at the expense of performance. In this paper, we describe a number of techniques which are currently used when designing low power, high performance microprocessors. These include fabrication process, circuit technology, and microprocessor architecture. Since most techniques result in complex tradeoffs, we will show how decisions regarding the selection of a low power design approach require careful consideration.


Power Consumption Power Management Very Long Instruction Word Dynamic Voltage Scaling Power Management Scheme 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Seong-Won Lee
    • 1
  • Neungsoo Park
    • 2
  • Jean-Luc Gaudiot
    • 3
  1. 1.Dept. of Computer EngineeringKwangwoon UniversitySeoulKorea
  2. 2.Dept. of Computer EngineeringKonkuk UniversitySeoulKorea
  3. 3.Dept. of Electrical Engineering and Computer ScienceUniversity of CaliforniaIrvineUSA

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