An Efficient Delay Metric on RC Interconnects Under Saturated Ramp Inputs
This paper presents a simple and fast delay metric RC-class interconnects under step and saturated ramp inputs. The proposed RC delay metric under step input, called MECM(Modified ECM), provides a reasonable accuracy without using circuit moments. The next RC delay metric under saturated ramp inputs, called FDM(Fast Delay Metric), can estimate delay times at an arbitrary node using a simple closed-form expression and is extended from MECM easily. As compared with similar techniques proposed in previous researches, it is shown that the FDM technique involves much lower computational complexity for a similar accuracy. As the number of circuit nodes increases, there will be a significant difference in estimation times of RC delay between the previous techniques based on two circuit moments and the FDM which do not depend on circuit moments.
KeywordsStep Input Estimate Delay Time Circuit Node Ramp Input Place Route
Unable to display preview. Download preview PDF.
- 2.Kay, R., Pileggi, L.T.: PRIMO: Probability interpretation of moments for delay calculation. In: Proc. IEEE/ACM Design Automation Conference, June 1998, pp. 463–468 (1998)Google Scholar
- 3.Lin, T., Acar, E., Pileggi, L.T.: h-gamma: An RC delay metric based on a gamma distribution approximation to the homogeneous response. In: Proc. IEEE/ACM Int. Conf. Computer-Aided Design, November 1998, pp. 19–25 (1998)Google Scholar
- 5.Menezes, N., Pullela, S., Dartu, F., Pillage, L.T.: RC Interconnect Synthesis - A Moment Fitting Approach. In: Proc. IEEE/ACM Intl. Conf. Computer-Aided Design, November 1994, pp. 418–425 (1994)Google Scholar
- 6.Kahng, A.B., Muddu, S.: Analysis of RC Interconnections Under Ramp Input. UCLA CS Dept. TR-960013 (April 1996)Google Scholar
- 7.Kashyap, C.V., Alpert, C.J., Liu, F., Devgan, A.: Closed Form Expressions for Extending Step Delay and Slew Metrics to Ramp Inputs. In: ACM/SIGDA 2003 International Symposium on Physical Design (April 2003)Google Scholar
- 8.O’Brien, P.R., Savarino, T.L.: Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation. In: Proc. IEEE/ACM Int. Conf. Computer-Aided Design, November 1989, pp. 512–515 (1989)Google Scholar
- 9.Qian, J., Pullela, S., Pillage, L.T.: Modeling the “Effective Capacitance” for the RC Interconnect of CMOS Gates. IEEE Trans. on Computer-Aided Design of Integrated Circuits and System 13(12) (December 1994)Google Scholar
- 10.Kahng, A.B., Muddu, S.: Efficient Gate Delay Modeling for Large Interconnect Loads. In: IEEE Multi-Chip Module Conf. (February 1996)Google Scholar
- 11.Gupta, R., Tutuianu, B., Pileggi, L.T.: The Elmore Delay as a Bound for RC Trees with Generalized Input Signals. In: ACM/IEEE Design Automation Conference, June 1995, pp. 364–369 (1995)Google Scholar
- 13.Ratzlaff, C.L., Gopal, N., Pillage, L.T.: RICE: Rapid interconnect circuit evaluator. In: Proc. IEEE/ACM Design Automation Conf., June 1991, pp. 555–560 (1991)Google Scholar