A Minimized Test Pattern Generation Method for Ground Bounce Effect and Delay Fault Detection

  • MoonJoon Kim
  • JeongMin Lee
  • WonGi Hong
  • Hoon Chang
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3983)


An efficient board-level interconnect test algorithm is proposed considering both the ground bounce effect and the delay faults detection. The proposed algorithm is capable of IEEE 1149.1 interconnect test, negative ground bounce effect prevention, and also detects delay faults as well. The number of final test pattern set is not much different with the previous method, even our method enables to detect the delay faults in addition to the abilities the previous method guarantees.


Test Pattern Delay Fault Board Level Test Pattern Generation Test Generation Algorithm 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • MoonJoon Kim
    • 1
  • JeongMin Lee
    • 1
  • WonGi Hong
    • 1
  • Hoon Chang
    • 2
  1. 1.Department of Computing, Graduate SchoolSoongsil UniversitySeoulKorea
  2. 2.School of ComputingSoongsil UniversitySeoulKorea

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