Easy Parameterized Verification of Biphase Mark and 8N1 Protocols

  • Geoffrey M. Brown
  • Lee Pike
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3920)


The Biphase Mark Protocol (BMP) and 8N1 Protocol are physical layer protocols for data transmission. We present a generic model in which timing and error values are parameterized by linear constraints, and then we use this model to verify these protocols. The verifications are carried out using SRI’s SAL model checker that combines a satisfiability modulo theories decision procedure with a bounded model checker for highly-automated induction proofs of safety properties over infinite-state systems. Previously, parameterized formal verification of real-time systems required mechanical theorem-proving or specialized real-time model checkers; we describe a compelling case-study demonstrating a simpler and more general approach. The verification reveals a significant error in the parameter ranges for 8N1 given in a published application note [1].


Decision Procedure Settling Time Receiver Clock Timeout Period Clock Jitter 


  1. 1.
    Maxim Integrated Products, Inc. Determining Clock Accuracy Requirements for UART Communications (June 2003), available at http://www.maxim-ic.com/appnotes.cfm/appnotenumber/2141
  2. 2.
    Moore, J.S.: A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol. Formal Aspects of Computing 6(1), 60–91 (1994)MathSciNetCrossRefMATHGoogle Scholar
  3. 3.
    Hung, D.V.: Modelling and verification of biphase mark protocols using PVS. In: Proceedings of the International Conference on Applications of Concurrency to System Design (CSD 1998), pp. 88–98. IEEE Computer Society Press, Los Alamitos (1998)CrossRefGoogle Scholar
  4. 4.
    Ivanov, S., Griffioen, W.O.D.: Verification of a biphase mark protocol. Technical Report CSI-R9915, University of Nijmegen Computing Science Institute (1999)Google Scholar
  5. 5.
    Henzinger, T., Preussig, J., Wong-Toi, H.: Some lessons from the Hytech experience. In: Proceedings of the 40th Annual Conference on Decision and Control, pp. 2887–2892 (2001)Google Scholar
  6. 6.
    Vaandrager, F.W., de Groot, A.L.: Analysis of a Biphase Mark Protocol with Uppaal and PVS. Technical Report NIII-R0455, Nijmegen Institute for Computing and Information Science (2004)Google Scholar
  7. 7.
    de Moura, L., Owre, S., Rueß, H., Rushby, J., Shankar, N., Sorea, M., Tiwari, A.: SAL 2. In: Alur, R., Peled, D.A. (eds.) CAV 2004. LNCS, vol. 3114, pp. 496–500. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  8. 8.
    de Moura, L., Rueß, H., Sorea, M.: Bounded model checking and induction: From refutation to verification. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 14–26. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  9. 9.
    de Moura, L., Owre, S., Rueß, H., Rushby, J., Shankar, N.: The ICS decision procedures for embedded deduction. In: Basin, D., Rusinowitch, M. (eds.) IJCAR 2004. LNCS (LNAI), vol. 3097, pp. 218–222. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  10. 10.
    Dutertre, B., Sorea, M.: Timed systems in SAL. Technical Report SRISDL-04-03, SRI International (2004)Google Scholar
  11. 11.
    Dutertre, B., Sorea, M.: Modeling and verification of a fault-tolerant realtime startup protocol using calendar automata. In: FORMATS/FTRTFT, pp. 199–214 (2004)Google Scholar
  12. 12.
    Rushby, J.: Verification diagrams revisited: Disjunctive invariants for easy verification. In: Emerson, E.A., Sistla, A.P. (eds.) CAV 2000. LNCS, vol. 1855. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  13. 13.
    Annichini, A., Bouajjani, A., Sighireanu, M.: TREX: A tool for reachability analysis of complex systems. In: Berry, G., Comon, H., Finkel, A. (eds.) CAV 2001. LNCS, vol. 2102, pp. 368–372. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  14. 14.
    Pike, L., Johnson, S.D.: The formal verification of a reintegration protocol. In: EMSOFT 2005: Proceedings of the 5th ACM international conference on Embedded software, pp. 286–289. ACM Press, New York (2005)Google Scholar
  15. 15.
    Brown, G.M.: Verification of a data synchronization circuit for all time (Unpublished) (2005)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2006

Authors and Affiliations

  • Geoffrey M. Brown
    • 1
  • Lee Pike
    • 2
  1. 1.Indiana UniversityBloomingtonUSA
  2. 2.Galois ConnectionsUSA

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