Criticality Driven Energy Aware Speculation for Speculative Multithreaded Processors

  • Rahul Nagpal
  • Anasua Bhowmik
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3769)


Speculative multithreaded architecture (SpMT) philosophy relies on aggressive speculative execution for improved performance. Aggressive speculative execution results in a significant wastage of dynamic energy due to useless computation in the event of mis-speculation. As energy consumption is becoming an important constraint in microprocessor design, it is extremely important to reduce such wastage of dynamic energy in SpMT processors in order to achieve a better performance to power ratio. Dynamic instruction criticality information can be effectively applied to control aggressive speculation in SpMT processors. In this paper, we present a model of micro-execution for SpMT processors to determine dynamic instruction criticality. We also present two novel techniques utilizing criticality information, namely delaying non-critical loads and criticality based thread-prediction for reducing useless computation and energy consumption. Our experiments show 17.71% and 11.63% reduction in dynamic energy for criticality based thread prediction and criticality based delayed load scheme respectively while the corresponding improvements in dynamic energy delay products are 13.93% and 5.54%.


Critical Path Power Ratio Dynamic Energy Superscalar Processor Energy Delay Product 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Fields, B., Rubin, S., Bodik, R.: Focusing Processor Policies via Critical-path Prediction. In: Proc. of Intl. Symp. on Computer Architecture (2001)Google Scholar
  2. 2.
    Franklin, M.: Multiscalar Processors. Kluwer Academic Publishers, Dordrecht (2002)Google Scholar
  3. 3.
    Tune, E., Tullsen, D.M., Calder, B.: Quantifying Instruction Criticality. In: Proc. of Intl. Conf. on Parallel Architectures and Compilation Techniques (2002)Google Scholar
  4. 4.
    Manne, S., Klauser, A., Grunwald, D.: Pipeline Gating: Speculation Control For Energy Reduction. In: Proc. of Intl. Symp. on Computer Architecture (1998)Google Scholar
  5. 5.
    Grunwald, D., Klauser, A., Manne, S., Pleszkun, A.: Confidence Estimation for Speculation Control. In: Proc. of Intl. Symp. on Computer Architecture (1998)Google Scholar
  6. 6.
    Jacobsen, E., Rotenberg, E., Smith, J.E.: Assigning Confidence to Conditional Branch Predictions. In: Proc. of Intl. Symp. on Microarchitecture (1996)Google Scholar
  7. 7.
    Aragon, J.L., Gonzalez, J., Gonzalez, A.: Power-Aware Control Speculation Through Selective Throttling. In: Proc. of Intl. Symp. on High Performance Computer Architecture (2003)Google Scholar
  8. 8.
    Ascia, G., Catania, V., Palesi, M., Patti, D.: A System-level Framework for Evaluating Area/Performance/Power Trade-offs of VLIW-based Embedded Systems. In: Asia and South Pacific Design Automation Conference (2005)Google Scholar
  9. 9.
    Seng, J.S., Tune, E.S., Tullsen, D.M.: Reducing Power with Dynamic Critical Path Information. In: Proc. of Intl. Symp. of Microarchitecture (2001)Google Scholar
  10. 10.
    Nagpal, R., Bhowmik, A.: Criticality Based Speculation Control for Speculative Multithreaded Architectures. In: Cao, J., Nejdl, W., Xu, M. (eds.) APPT 2005. LNCS, vol. 3756, pp. 31–40. Springer, Heidelberg (2005)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Rahul Nagpal
    • 1
  • Anasua Bhowmik
    • 2
  1. 1.Department of Computer Science and AutomationIndian Institute of ScienceBangaloreIndia
  2. 2.AMD-India Engineering CenterMicroprocessor Solutions SectorBangaloreIndia

Personalised recommendations