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Performance and Power Evaluation of an Intelligently Adaptive Data Cache

  • Domingo Benítez
  • Juan Carlos Moure
  • Dolores Isabel Rexachs
  • Emilio Luque
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3769)

Abstract

We describe the analysis of an on-line pattern-recognition algorithm to dynamically control the configuration of the L1 data cache of a high-performance processor. The microarchitecture achieves higher performance and energy saving due to the accommodation of operating frequency, capacity, set-associativity, line size, hit latency, energy per access, and chip area to program workload and ILP. We show that for the operating frequency 4.5 GHz, the execution time is always reduced with an average measure of 12.1% when compared to a non-adaptive high-performance processor. Additionally, the energy saving is 2.7% on average, and t1he product time-energy is reduced on average by 14.9%. We also consider a profile-based reconfiguration of data cache, which allows picking different cache configurations but only one can be chosen for each program. Experimental results indicate that this approach yields a high percentage of the performance improvement and energy saving achieved by the on-line algorithm.

Keywords

Dynamic Adaptation Chip Area Data Cache Line Size Baseline Configuration 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Domingo Benítez
    • 1
  • Juan Carlos Moure
    • 2
  • Dolores Isabel Rexachs
    • 2
  • Emilio Luque
    • 2
  1. 1.DIS Department & IUSIANIUniversity of Las Palmas G.C.Las PalmasSpain
  2. 2.Computer Architecture and Operating Systems (CAOS) DepartmentUniversidad Autónoma de BarcelonaBarcelonaSpain

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