Abstract
As silicon CMOS technology is scaled into the nanometer regime, a whole system can be integrated into one chip. At the same time, the computer-aided design technology is challenged by two major features: the ever-increasing design complexity of gigascale integration and complicated physical effects inherent from the nanoscale technology. In this paper, a new methodology of integrating High Level Synthesis and Floorplan together is presented. The whole design flow is divided into two phases: a fast searching space scan procedure and a detailed solution optimize procedure. The searching space of integrating HLS and Floorplan is first “smoothed” by a “Behavior Information based Cluster Algorithm”, and then a fast scan of this smoothed searching space is proceeded. The result of the first phrase will be used as the start point of the detailed optimize procedure. The experimental result show that the methodology is efficient.
This work is mainly supported by NSFC 90407005 and partially supported by NSFC 90207017 and NSFC 60236020.
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Wang, Y., Bian, J., Hong, X., Yang, L., Zhou, Q., Wu, Q. (2005). A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. In: Yang, L.T., Zhou, X., Zhao, W., Wu, Z., Zhu, Y., Lin, M. (eds) Embedded Software and Systems. ICESS 2005. Lecture Notes in Computer Science, vol 3820. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11599555_28
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DOI: https://doi.org/10.1007/11599555_28
Publisher Name: Springer, Berlin, Heidelberg
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