Design and Implementation of IEEE 802.11i Architecture for Next Generation WLAN
The drive for high data rate and QoS support in wireless LANs has pushed the IEEE to develop IEEE 802.11n and IEEE 802.11e. For higher throughput, new MAC mechanisms such as Block Ack in IEEE 802.11e and frame aggregation in IEEE 802.11n are being currently discussed and these mechanisms needs short response time in each MPDU processing. In this paper, we propose a design of IEEE 802.11i hardware architecture to support these new MAC mechanisms. We reduce the response time in the crypto engine to short constant interval by using the dual S-Box scheme in WEP and TKIP processing and by adopting parallel structure in CCMP. In our method, the key management block is used to eliminate the computational burden for key and per-packet counter management in 802.11i device driver. Our design features 195 Mbps in WEP, TKIP, and 562 Mbps in CCMP throughput respectively at 50 MHz frequency, which are targeted to Altera Stratix FPGA device.
KeywordsClock Cycle Device Driver Data Throughput Payload Size Frame Aggregation
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