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Artificial Neural Network Engine: Parallel and Parameterized Architecture Implemented in FPGA

  • Milene Barbosa Carvalho
  • Alexandre Marques Amaral
  • Luiz Eduardo da Silva Ramos
  • Carlos Augusto Paiva da Silva Martins
  • Petr Ekel
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3776)

Abstract

In this paper we present and analyze an artificial neural network hardware engine, its architecture and implementation. The engine was designed to solve performance problems of the serial software implementations. It is based on a hierarchical parallel and parameterized architecture. Taking into account verification results, we conclude that this engine improves the computational performance, producing speedups from 52.3 to 204.5 and its architectural parameterization provides more flexibility.

Keywords

Artificial Neural Network FPGA Implementation Solve Performance Problem Neuron Module Temporal Parallelism 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Milene Barbosa Carvalho
    • 1
  • Alexandre Marques Amaral
    • 1
  • Luiz Eduardo da Silva Ramos
    • 1
    • 2
  • Carlos Augusto Paiva da Silva Martins
    • 1
  • Petr Ekel
    • 1
  1. 1.Pontifical Catholic University of Minas GeraisBrazil
  2. 2.Rutgers University (USA)Belo HorizonteBrazil

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