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Performance Modelling and Optimization of Memory Access on Cellular Computer Architecture Cyclops64

  • Yanwei Niu
  • Ziang Hu
  • Kenneth Barner
  • Guang R. Gao
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3779)

Abstract

This paper focuses on the Cyclops64 computer architecture and presents an analytical model and performance simulation results for the preloading and loop unrolling approaches to optimize the performance of SVD (Singular Value Decomposition) benchmark. A performance model for dissecting the total execution cycles is presented. The data preloading using “memcpy” or hand optimized “inline” assembly code, and the loop unrolling approach are implemented and compared with each other in terms of the total number of memory access cycles. The key idea is to preload data from offchip to onchip memory and store the data back after the computation. These approaches can reduce the total memory access cycles and can thus improve the benchmark performance significantly.

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Copyright information

© IFIP International Federation for Information Processing 2005

Authors and Affiliations

  • Yanwei Niu
    • 1
  • Ziang Hu
    • 1
  • Kenneth Barner
    • 1
  • Guang R. Gao
    • 1
  1. 1.Department of ECEUniversity of DelawareNewarkUSA

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