Abstract
Moore’s law describes the growth in on-chip transistor density, which doubles every 18 to 24 months and looks set to continue for at least a decade and possibly longer. This growth poses major problems (and provides opportunities) for computer architecture in this time frame. The problems arise from current architectural approaches, which do not scale well and have used clock speed rather than concurrency to increase performance. This, in turn, causes excessive power dissipation and circuit complexity. This paper takes a long-range position on the future of chip multiprocessors, both from the micro-architecture perspective, as well as from a systems perspective. Concurrency will come from many levels, with instruction and loop-level concurrency managed at the micro-architecture and higher levels by the system. Chip-level multiprocessors exploiting massive concurrency we term Microgrids. The directions proposed in this paper provide micro-architectural concurrency with full forward compatibility over orders of magnitude of scaling and also the management of on-chip resources (processors etc.) so as to autonomously configure a system for a variety of goals (e.g. low power, high performance, etc.).
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Jesshope, C.: Micro-grids - the exploitation of massive on-chip concurrency, invited paper, Cetraro HPC workshop, Cetraro, Italy, to be published in Advances in Parallel Computing (2004), http://staff.science.uva.nl/~jesshope/Papers/HPC-paper.pdf
Anderson, D.W., Sparacio, F.J., Tomasulo, R.M.: The IBM System/360 Model 91: Machine Philosophy and Instruction-Handling. IBM J. Res. Dev. 11(1), 8 (1967)
Smith, J., Pleszkun, A.: Implementation of Precise Interrupts in Pipelined Processors. In: Proc. of Int’l. Symposium on Computer Architecture, pp. 36–44 (1985)
Kucuk, G., Ponomarev, D., Ghose, K., Kogge, P.M.: Energy–Efficient Instruction Dispatch Buffer Design. In: Int’l. Symp. on Low Power Electronics and Design (ISLPED 2001) (August 2001)
Balasubramonian, R., Dwarkadas, S., Albonesi, D.: Reducing the Complexity of the Register File in Dynamic Superscalar Processor. In: Proc. of the 34th Int’l. Symposium on Microarchitecture (MICRO 2001), p. 37 (2001)
Shilov, A.: Intel to Cancel NetBurst, Pentium 4, Xeon Evolution (2004), http://www.xbitlabs.com/news/cpu/display/20040507000306.html (accessed January 7, 2005)
Wilcox, K., Manne, S.: Alpha processors: A history of power issues and a look to the future, Cool-Chips Tutorial, Held in conjunction with MICRO-32 (November 1999)
Homewood, M., May, D., Shepherd, D., Shepherd, R.: The IMS T800 Transputer. IEEE Micro, 10–26 (October 1987)
Otten, R.H.J.M., Stravers, P.: Challenges in physical chip design. In: Proc. ICCAD 2000, p. 84. IEEE Computer society press, San Jose (2000)
Ronen, R., Mendelson, A., Lai, K., Pollack, F., Shen, J.: Coming challenges in Microarchitecture and architecture. Proc IEEE 89(3), 325–340 (2001)
Bolychevsky, A., Jesshope, C.R., Muchnick, V.B.: Dynamic scheduling in RISC architectures. IEE Trans. E, Computers and Digital Techniques 143, 309–317 (1996)
Gontmakher, A., Schuster, A.: Intrathreads: Techniques for Parallelizing Sequential Code. In: 6th Workshop on Multithreaded Execution, Architecture, and Compilation (MTEAC-6), Istanbul (November 2002) (in conjunction with Micro-35)
Jesshope, C.R., Luo, B.: Micro-threading: A New Approach to Future RISC. In: Proc. ACAC 2000, Canberra, Canberra, January 2000, pp. 34–41. IEEE Computer Society press, Los Alamitos (2000) ISBN 0-7695-0512-0
Jesshope, C.R.: Implementing an efficient vector instruction set in a chip multi-processor using micro-threaded pipelines. In: Proc. ACSAC 2001, Australia Computer Science Communications, vol. 23(4), pp. 80–88. IEEE Computer Society, Los Alamitos (2001) ISBN 0-7695-0954-1
Luo, B., Jesshope, C.: Performance of a Micro-threaded Pipeline. In: Lai, F., Morris, J. (eds.) Proc. 7th Asia-Pacific conference on Computer systems architecture, vol. 6, pp. 83–90. Australian Computer Society, Inc., Darlinghurst (2002) ISBN ~ ISSN:1445-1336 , 0-909925-84-4
Jesshope, C.R.: Multithreaded microprocessors – evolution or revolution (Keynote paper). In: Omondi, A.R., Sedukhin, S.G. (eds.) ACSAC 2003. LNCS, vol. 2823, pp. 21–45. Springer, Heidelberg (2003) ISSN0302-9743
Jesshope, C.R.: Scalable instruction-level parallelism. In: Pimentel, A.D., Vassiliadis, S. (eds.) SAMOS 2004. LNCS, vol. 3133, pp. 383–392. Springer, Heidelberg (2004)
Brockman, J.B., Thoziyoor, S., Kuntz, S.K., Kogge, P.M.: A low cost, multithreaded processing-in-memory system. In: Proc. 3rd workshop on Memory performance issues (ISCA 31), pp. 16–22 (2004) ISBN:1-59593-040-X
Foster, I., Roy, A., Sander, V.: A Quality of Service Architecture that Combines Resource Reservation and Application Adaptation. In: Proc. 8th International Workshop on Quality of Service (IWQOS 2000), Pittsburgh, USA (2000)
Buyya, R., Murshed, M.: GridSim: A Toolkit for the Modeling and Simulation of Distributed Resource Management and Scheduling for Grid Computing. Journal of Concurrency and Computation: Practice and Experience (CCPE) 14(13-15) (November-December 2002)
Manne, S., Klauser, A., Grunwald, D.: Pipeline Gating: Speculation Control for Energy Reduction. In: Proc. Intl Symp. on ComputerArchitecture, ISCA (1998)
Marculescu, D.: Profile driven Code Execution for Low Power Dissipation. In: Proc. Intl. Symp. Low Power Electronics and Design (2000)
Zyuban, V., Kogge, P.: Optimization of High-Performance Superscalar Architectures for Energy-Delay Product. In: Proc Intl. Symposium on Low Power Electronics and Design (2000)
Ghiasi, S., Casmira, J., Grunwald, D.: Using IPC Variation in Workloads with Externally Specified Rates to Reduce Power Consumption. In: Workshop on Complexity Effective Design. ISCA27 (2000)
Iyer, A., Marculescu, D.: Power aware microarchitecture resource scaling. In: Proc Design, automation and test in Europe, Munich, Germany, pp. 190–196 (2001) ISBN:0-7695-0993-2
Sree, R., Settle, A., Bratt, I., Connors, D.A. (2003) Compiler-directed resource management for active code region. In: Proc. 7th Workshop on Interaction between Compilers and Computer Architecture (February 2003)
Chheda, S., Unsal, O., Koren, I., Krishna, C.M., Moritz, C.A.: Combining compiler and runtime IPC predictions to reduce energy in next generation architectures. In: Proc. 1st Conf. On Computing Frontiers archive, Ischia, Italy, pp. 240–254 (2004) ISBN:1-58113-741-9
Shafarenko, A., Scholz, S.-B.: General homomorphic overloading. In: Grelck, C., Huch, F., Michaelson, G.J., Trinder, P. (eds.) IFL 2004. LNCS, vol. 3474, pp. 195–210. Springer, Heidelberg (2005)
Shafarenko, A.: Stream Processing on the Grid: an Array Stream Transforming Language. SNPD 2003, 268–276 (2003)
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Bousias, K., Jesshope, C. (2005). The Challenges of Massive On-Chip Concurrency. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_14
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DOI: https://doi.org/10.1007/11572961_14
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