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Formalization of the DE2 Language

  • Warren A. HuntJr.
  • Erik Reeber
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3725)

Abstract

We formalized the DE2 hierarchical, occurrence-oriented finite state machine (FSM) language, and have developed a proof theory allowing the mechanical verification of FSM descriptions. Using the ACL2 functional logic, we have defined a predicate for detecting the well-formedness of DE2 expressions. Furthermore, we have defined a symbolic simulator for DE2 expressions which also serves as a formal cycle-based semantics for the DE2 language. DE2 is deeply embedded within ACL2, and the DE2 language includes an annotation facility that can be used by programs that manipulate DE2 descriptions. The DE2 user may also specify and prove the correctness of programs that generate DE2 descriptions. We have used DE2 to mechanically verify components of the TRIPS microprocessor implementation.

Keywords

Finite State Machine Hardware Description Language Primitive Module Deep Embedding Lambda Module 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Bjesse, P., Claessen, K., Sheeran, M., Singh, S.: Lava: Hardware Design in Haskell. In: The International Conference on Functional Programming (ICFP), vol. 32(1), pp. 174–184. ACM Press, New York (1998)CrossRefGoogle Scholar
  2. 2.
    Sheeran, M.: Generating Fast Multipliers Using Clever Circuits. In: Hu, A.J., Martin, A.K. (eds.) FMCAD 2004. LNCS, vol. 3312, pp. 6–20. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  3. 3.
    Krstic, S., Matthews, J.: Semantics of the reFLect Language. In: Principles and Practice of Declarative Programming (PPDP), pp. 32–42. ACM Press, New York (2004)Google Scholar
  4. 4.
    Aagaard, M.D., Jones, R.B., Seger, C.-J.H.: Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving. In: Bertot, Y., Dowek, G., Hirschowitz, A., Paulin, C., Théry, L. (eds.) TPHOLs 1999. LNCS, vol. 1690, p. 323. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  5. 5.
    Aagaard, M.D., Jones, R.B., O’Leary, J.W., Seger, C.-J.H., Melham, T.F.: A methodology for large-scale hardware verification. In: Johnson, S.D., Hunt Jr., W.A. (eds.) FMCAD 2000. LNCS, vol. 1954, pp. 263–282. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  6. 6.
    Sethumadhavan, S., Desikan, R., Burger, D., Moore, C.R., Keckler, S.W.: Scalable Hardware Memory Disambiguation for High ILP Processors (Load/Store Queue Design). In: 36th International Symposium on Microarchitecture (MICRO 36), pp. 399–410 (2003)Google Scholar
  7. 7.
    The Tera-op Reliable Intelligently adaptive Processing System(TRIPS), http://www.cs.utexas.edu/users/cart/trips/
  8. 8.
    Brock, B., Kaufmann, M., Moore, J.: ACL2 Theorems about Commercial Microprocessors. In: Srivas, M., Camilleri, A. (eds.) FMCAD 1996. LNCS, vol. 1166, pp. 275–293. Springer, Heidelberg (1996)CrossRefGoogle Scholar
  9. 9.
    Sawada, J.: Formal Verification of an Advanced Pipelined Machine. PhD Thesis, University of Texas at Austin (1999)Google Scholar
  10. 10.
    Hunt Jr., W.A.: The DE Language. In: Computer-aided Reasoning: ACL2 case studies, pp. 151–166. Kluwer Academic Publishers, Dordrecht (2000)Google Scholar
  11. 11.
    Boyer, R.S., Moore, J.S.: A Computational Logic Handbook. Academic Press, Boston (1988)zbMATHGoogle Scholar
  12. 12.
    Gordon, M.J.C., Melham, T.F. (eds.): Introduction to HOL: A Theorem Proving Environment for Higher-Order Logic. Cambridge University Press, Cambridge (1993)zbMATHGoogle Scholar
  13. 13.
    Boulton, R., Gordon, A., Gordon, M., Harrison, J., Herbert, J., Van Tassel, J.: Experience with Embedding Hardware Description Languages in HOL. In: Theorem Provers in Circuit Design, IFIP Transactions A-10, pp. 129–156. Elsevier Science Publishers, Amsterdam (1992)Google Scholar
  14. 14.
    Gordon, M.: Why Higher-order Logic is a Good Formalism for Specifying and Verifying Hardware. Technical Report 77, University of Cambridge, Computer Laboratory (1985)Google Scholar
  15. 15.
    Hunt Jr., W.A., Brock, B.C.: A Formal HDL and Its Use in the FM9001 Verification. In: Hoare, C.A.R., Gordon, M.J.C. (eds.) Mechanized Reasoning and Hardware Design. Prentice-Hall International Series in Computer Science, pp. 35–48 (1992)Google Scholar
  16. 16.
    Kaufmann, M., Moore, J.S.: ACL2: An Industrial Strength Version of NQTHM. In: Eleventh Annual Conference on Computer Assurance (COMPASS 1996), pp. 23–34. IEEE Computer Society Press, Los Alamitos (1996)CrossRefGoogle Scholar
  17. 17.
    Steele, G.: Common Lisp: The Lanugage, 2nd edn. Digital Press (1990)Google Scholar
  18. 18.
    Windley, P.J., Coe, M.L.: A Correctness Model for Pipelined Microprocessors. In: Kumar, R., Kropf, T. (eds.) TPCD 1994. LNCS, vol. 901, pp. 33–51. Springer, Heidelberg (1995)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Warren A. HuntJr.
    • 1
  • Erik Reeber
    • 1
  1. 1.Department of Computer SciencesThe University of TexasAustinUSA

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