A Non-redundant and Efficient Architecture for Karatsuba-Ofman Algorithm
The divide-and-conquer method is efficiently used in parallel multiplier over finite field GF(2 n ). Leone proposed optimal stop condition for iteration of Karatsuba-Ofman algorithm (KOA). Multi-segment Karatsuba method (MSK) is proposed by Ernst et al. In this paper, we propose a Non-Redundant Karatsuba-Ofman algorithm (NRKOA) with removing redundancy operations, and design a parallel hardware architecture based on the proposed algorithm. Comparing with existing related Karatsuba architectures with the same time complexity, the proposed architecture reduces the area complexity. The proposed NRKOA multiplier has more efficient the space complexity than the previous KOA multipliers, where n is a prime. Furthermore, the space complexity of the proposed multiplier is reduced by 43% in the best case.
KeywordsPolynomial Multiplication Karatsuba-Ofman Algorithm Non-Redundant Karatsuba-Ofman Algorithm Hardware Architecture
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