AES on FPGA from the Fastest to the Smallest

  • Tim Good
  • Mohammed Benaissa
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3659)

Abstract

Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to be the fastest, achieving 25 Gbps throughput using a Xilinx Spartan-III (XC3S2000) device. The second is believed to be the smallest and fits into a Xilinx Spartan-II (XC2S15) device, only requiring two block memories and 124 slices to achieve a throughput of 2.2 Mbps. These designs show the extremes of what is possible and have radically different applications from high performance e-commerce IPsec servers to low power mobile and home applications. The high speed design presented here includes support for continued throughput during key changes for both encryption and decryption which previous pipelined designs have omitted.

Keywords

Advanced Encryption Standard (AES) Field Programmable Gate Array (FPGA) finite field design exploration high throughput pipelined low area Application Specific Instruction Processor (ASIP) 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Tim Good
    • 1
  • Mohammed Benaissa
    • 1
  1. 1.Department of Electronic & Electrical EngineeringUniversity of SheffieldSheffieldUK

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