Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3659)


During the last years, several logic styles that counteract side-channel attacks have been proposed. They all have in common that their level of resistance heavily depends on implementation constraints that are costly to satisfy. For example, the capacitive load of complementary wires in an integrated circuit may need to be balanced. This article describes a novel side-channel analysis resistant logic style called MDPL that completely avoids such constraints. It is a masked and dual-rail pre-charge logic style and can be implemented using common CMOS standard cell libraries. This makes MDPL perfectly suitable for semi-custom designs.


Side-Channel Analysis DPA Hardware Countermeasures MDPL Masking Logic Dual-Rail Pre-Charge Logic 


  1. 1.
  2. 2.
    Bock, H., Bucci, M., Luzzi, R.: An Offset-Compensated Oscillator-Based Random Bit Source for Security Applications. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 268–281. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  3. 3.
    Chari, S., Jutla, C.S., Rao, J.R., Rohatgi, P.: Towards Sound Approaches to Counteract Power-Analysis Attacks. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 398–412. Springer, Heidelberg (1999)Google Scholar
  4. 4.
    Feldhofer, M., Dominikus, S., Wolkerstorfer, J.: Strong Authentication for RFID Systems using the AES Algorithm. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 357–370. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  5. 5.
    Fournier, J.J.A., Moore, S., Li, H., Mullins, R.D., Taylor, G.S.: Security Evaluation of Asynchronous Circuits. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 137–151. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  6. 6.
    Goubin, L., Patarin, J.: DES and Differential Power Analysis – The Duplication Method. In: Koç, Ç.K., Paar, C. (eds.) CHES 1999. LNCS, vol. 1717, pp. 158–172. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  7. 7.
    Klug, F., Kniffler, O., Gammel, B.: Rechenwerk, Verfahren zum Ausführen einer Operation mit einem verschlüsselten Operanden, Carry-Select-Addierer und Kryptographieprozessor. German Patent DE 10201449 C1 (January 2002)Google Scholar
  8. 8.
    Kocher, P.C., Jaffe, J., Jun, B.: Differential Power Analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)Google Scholar
  9. 9.
    Mangard, S., Popp, T., Gammel, B.M.: Side-Channel Leakage of Masked CMOS Gates. In: Menezes, A. (ed.) CT-RSA 2005. LNCS, vol. 3376, pp. 351–365. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  10. 10.
    Menicocci, R., Pascal, J.: Elaborazione Crittografica di Dati Digitali Mascherati. Italian Patent IT MI0020031375A (July 2003)Google Scholar
  11. 11.
    Messerges, T.S., Dabbish, E.A., Puhl, L.: Method and Apparatus for Preventing Information Leakage Attacks on a Microelectronic Assembly. US Patent 6,295,606 (September 2001), Available online at,
  12. 12.
    Messerges, T.S., Dabbish, E.A., Sloan, R.H.: Examining Smart-Card Security under the Threat of Power Analysis Attacks. IEEE Transactions on Computers 51(5), 541–552 (2002)CrossRefMathSciNetGoogle Scholar
  13. 13.
    Moore, S., Anderson, R.J., Cunningham, P., Mullins, R.D., Taylor, G.S.: Improving smart card security using self-timed circuits. In: Proceedings of the Eighth International Symposium on Asynchronous Circuits and Systems (ASYNC 2002), pp. 211–218. IEEE Computer Society, Los Alamitos (2002)CrossRefGoogle Scholar
  14. 14.
    National Institute of Standards and Technology (NIST). FIPS-197: Advanced Encryption Standard (November 2001), Available online at,
  15. 15.
    Rabaey, J.M.: Digital Integrated Circuits. Prentice-Hall, Englewood Cliffs (1996) ISBN 013-1786091Google Scholar
  16. 16.
    Sokolov, D., Murphy, J., Bystrov, A., Yakovlev, A.: Improving the Security of Dual-Rail Circuits. In: Joye, M., Quisquater, J.-J. (eds.) CHES 2004. LNCS, vol. 3156, pp. 282–297. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  17. 17.
    Suzuki, D., Saeki, M., Ichikawa, T.: Random Switching Logic: A Countermeasure against DPA based on Transition Probability. Cryptology ePrint Archive, Report 2004/346 (2004),
  18. 18.
    Tiri, K., Akmal, M., Verbauwhede, I.: A Dynamic and Differential CMOS Logic with Signal Independent Power Consumption to Withstand Differential Power Analysis on Smart Cards. In: 28th European Solid-State Circuits Conference (ESSCIRC 2002) (2002)Google Scholar
  19. 19.
    Tiri, K., Verbauwhede, I.: Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 137–151. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  20. 20.
    Tiri, K., Verbauwhede, I.: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Paris, France, February 16-20, 2004, pp. 246–251. IEEE Computer Society, Los Alamitos (2004)CrossRefGoogle Scholar
  21. 21.
    Tiri, K., Verbauwhede, I.: Place and Route for Secure Standard Cell Design. In: CARDIS 2004 - Sixth Smart Card Research and Advanced Application IFIP Conference, Toulouse, France, August 23-26 (2004)Google Scholar
  22. 22.
    Trichina, E.: Combinational Logic Design for AES SubByte Transformation on Masked Data. Cryptology ePrint Archive, Report 2003/236 (2003),
  23. 23.
    Weste, N.H.E., Eshraghian, K.: Principles of CMOS VLSI Design - A Systems Perspective, 2nd edn. Addison-Wesley, Reading (1993) ISBN 0-201-53376-6Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  1. 1.Institute for Applied Information Processing and Communications (IAIK)TU GrazGrazAustria

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