Abstract
When cryptosystems are being used in real life, hardware and software implementations themselves present a fruitful field for attacks. Side channel attacks exploit information such as time measurements, power consumption, and electromagnetic emission that leaks from a device when it executes cryptographic applications. When leaked information is correlated to a secret key, an adversary may be able to recover the key by monitoring this information. This paper describes an AES coprocessor that provides complete protection against first-order differential power analysis by embedding a widely used software countermeasure that decorrelates data being processed from the leaked information, so-called data masking, at a hardware level.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Akkar, M., Giraud, C.: An implementation of DES and AES, secure against some attacks. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 309–318. Springer, Heidelberg (2001)
Anderson, R., Kuhn, M.: Low cost attacks on tamper resistant devices. In: Christianson, B., Lomas, M. (eds.) Security Protocols 1997. LNCS, vol. 1361, pp. 125–136. Springer, Heidelberg (1998)
Blömmer, J., Merchan, J.G., Krummel, V.: Provably secure masking of AES. IACR Cryptology ePrint Archive Report 2004/101 (2004)
Bucci, M., Germani, L., Guglielmo, M., Luzzi, R., Trifiletti, A.: A simulation methodology for DPA resistance testing of cryptographic processors, (2003) (manuscript)
Chari, S., Jutla, C., Rao, J., Rohatgi, P.: Towards sound approaches to counteract power-analysis attacks. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 398–412. Springer, Heidelberg (1999)
Clavier, C., Coron, J.-S., Dabbous, N.: Differential power analysis in the presence of hardware countermeasures. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 252–263. Springer, Heidelberg (2000)
Daemen, J., Rijmen, V.: The design of Rijndael: AES - The Advanced Encryption Standard. Springer, Berlin (2002)
Gandolfi, K., Mourtel, C., Oliver, F.: Electromagnetic analysis: concrete results. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 251–261. Springer, Heidelberg (2001)
Goliç, J., Tymen, Ch.: Multiplicative masking and power analysis of AES. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 198–212. Springer, Heidelberg (2003)
Goubin, L.: A sound method for switching between boolean and arithmetic masking. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 3–15. Springer, Heidelberg (2001)
Kocher, P., Jaffe, J., Jun, B.: Differential power analysis. In: Wiener, M. (ed.) CRYPTO 1999. LNCS, vol. 1666, pp. 388–397. Springer, Heidelberg (1999)
Kocher, P.: Timing attacks on implementations of Diffie-Hellmann, RSA, DSS, and other systems. In: Koblitz, N. (ed.) CRYPTO 1996. LNCS, vol. 1109, pp. 104–113. Springer, Heidelberg (1996)
Kommerling, O., Kuhn, M.: Design principles for tamper-resistant smartcard processors. In: Proc. USENIX Workshop on Smartcard Technology (Smartcard 99), pp. 9–20 (1998)
Lu, C.C., Tseng, S.-Y.: Integrated design of AES (Advanced Encryption Srandard) encryptor and decryptor. In: Proc. IEEE conf. on Application-Specific Systems, Architectures, and Processors (ASAP 2002), pp. 277–285 (2002)
Mangard, S., Aigner, M., Dominikus, S.: A highly regular and scalable AES hardware architecture. IEEE Transactions on Computers 52(4), 483–491 (2003)
Mastrovito, E.D.: VLSI architectures for computations in Galois fields, PhD Thesis, Linkoping University, Linkoping, Sweden (1991)
Messerges, T.: Securing the AES finalists against power analysis attacks. In: Schneier, B. (ed.) FSE 2000. LNCS, vol. 1978, pp. 150–165. Springer, Heidelberg (2001)
Messerges, T.S., Dabbish, E.A., Sloan, R.H.: Examining smart-card security under the thread of power analysis. IEEE Trans. Computers 51(5), 522–541 (2002)
Messerges, T.S.: Using second-order power analysis to attack DPA resistant software. In: Paar, C., Koç, Ç.K. (eds.) CHES 2000. LNCS, vol. 1965, pp. 238–251. Springer, Heidelberg (2000)
Morioka, S., Satoh, A.: An optimized S-Box circuit architecture for low power AES design. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 172–186. Springer, Heidelberg (2003)
Moore, S., Anderson, R., Cunningham, P., Mullins, R., Taylor, G.: Improving smart card security using self-timed circuits. In: Proc. Proceeding 8th IEEE International Symposium on Asynchronous Circuits and Systems – ASYNC 2002, pp. 23–58. IEEE, Los Alamitos (2002)
Paar, C.: Efficient VLSI architectures for bit parallel computations in Galois fields. PhD Thesis, University of Essen, Germany (1994)
Quisquater, J.J., Samide, D.: Electromagnetic analysis (ema): measures and counter-measures for smart cards. In: Attali, S., Jensen, T. (eds.) E-smart 2001. LNCS, vol. 2140, pp. 200–210. Springer, Heidelberg (2001)
Rudra, A., Dubey, P., Julta, C., Kumar, V., Rao, J., Rohatgi, P.: Efficient Rijndael implementation with composite field arithmetic. In: Koç, Ç.K., Naccache, D., Paar, C. (eds.) CHES 2001. LNCS, vol. 2162, pp. 175–188. Springer, Heidelberg (2001)
Satoh, A., Morioka, S., Takano, K., Munetoh, S.: A compact Rijndael hardware architecture with S-Box optimization. In: Boyd, C. (ed.) ASIACRYPT 2001. LNCS, vol. 2248, pp. 239–254. Springer, Heidelberg (2001)
Tiri, K., Akmal, M., Verbauwhede, I.: A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. In: Proc. IEEE 28th Europen Solid-State Circuit Conf. – ESSCIRC 2002 (2002)
Trichina, E., De Seta, D., Germani, L.: Simplified Adaptive Multiplicative Masking for AES and its secure implementation. In: Kaliski Jr., B.S., Koç, Ç.K., Paar, C. (eds.) CHES 2002. LNCS, vol. 2523, pp. 277–285. Springer, Heidelberg (2003)
Trichina, E.: Combinational logic design for AES SubByte transformation on masked data. In: IACR Cryptology ePrint Archive (2003)
Wolkerstorfer, J.: An ASIC implementation of the AES MixColumn operation. In: Proceedings Austrochip 2001 (2001)
Wolkerstorfer, J., Oswald, E., Lamberger, M.: An ASIC implementation of the AES S-Boxes. In: Preneel, B. (ed.) CT-RSA 2002. LNCS, vol. 2271, pp. 67–78. Springer, Heidelberg (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Trichina, E., Korkishko, T., Lee, K.H. (2005). Small Size, Low Power, Side Channel-Immune AES Coprocessor: Design and Synthesis Results. In: Dobbertin, H., Rijmen, V., Sowa, A. (eds) Advanced Encryption Standard – AES. AES 2004. Lecture Notes in Computer Science, vol 3373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11506447_10
Download citation
DOI: https://doi.org/10.1007/11506447_10
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-26557-3
Online ISBN: 978-3-540-31840-8
eBook Packages: Computer ScienceComputer Science (R0)