Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design

  • Lijuan Luo
  • Qiang Zhou
  • Xianlong Hong
  • Hanbin Zhou
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 3483)

Abstract

Quadratic/Analytical placement methods have been widely used in the latest IC design process. This kind of placement needs a powerful detailed placement method for large-scale mixed macro and standard cell placement. An efficient and effective multi- stage iterative detailed placement (MSIP) algorithm is proposed in this paper. It combines a better initial placement based on combinatorial optimization method with a deterministic local search for post optimization. Various strategies are used for saving computation time. Experimental results show that it can get an average of 22% wire length improvement comparing to PAFLO [6] in comparable runtime.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Kahng, A.B., Tucker, P., Zelikovsky, A.: Optimization of linear placements for wirelength minimization with free sites. In: Proc. Of the Asia and South Pacific Design Automation Conference, pp. 241–244 (1999)Google Scholar
  2. 2.
    Caldewll, A.E., Kahng, A.B., Markov, I.L.: Optimal partitioners and end-case placers for standard-cell layout. In: Proc. ISPD 1999, pp. 90–94 (1999)Google Scholar
  3. 3.
    Srinivasan, A., Chaudhary, K., Kuh, E.S.: RITUAL: a performance driven placement algorithm. IEEE Trans. on Circuits and Systems II 39(11), 825–840 (1992)MATHCrossRefGoogle Scholar
  4. 4.
    Yao, B., Hou, W.T., Hong, X.L., Cai, Y.C.: FAME: A Fast Detailed Placement Algorithm for Standard_Cell Layout Based on Mixed Mincut and Enumeration. In: Proc. Int. Conf. On CAD/CG, Shanghai, pp. 616–621 (1999)Google Scholar
  5. 5.
    Chang, C.-C., Cong, J., Yuan, X.: Multi-level placement for large-scale mixed-size IC designs. In: Proc. Asia South Pacific Design Automation Conference, January 2003, pp. 325–330 (2003)Google Scholar
  6. 6.
    Zhou, H., Wu, W., Hong, X.: PAFLO: a fast standard-cell detailed placement algorithm. In: Proceeding of ICCAS 2002, pp. 1401–1405 (2002)Google Scholar
  7. 7.
    Yu, H., Hong, X., Cai, Y.: MMP: a novel placement algorithm for combined macro block and standard cell layout design. In: Proceeding of ASP-DAC, pp. 271–276 (2000)Google Scholar
  8. 8.
  9. 9.
    Vygen, J.: Algorithms for detailed placement of standard cells. In: Proc. of the Conference Design Automation and Test in Europe (DATE 1998), pp. 321–324. IEEE, Los Alamitos (1998)Google Scholar
  10. 10.
    Luo, L., Zhou, Q., Hong, X., Zhou, H.: Effective algorithm for optimal initial solution in mixed-mode detailed placement. In: ASICON 2003, pp. 170–173 (2003)Google Scholar
  11. 11.
    Sarrafzadeh, M., Wang, M.: NRG: global and detailed placement. In: Proc. of IEEE Intl. Conference on Computer Aided Design, pp. 532–537. IEEE Computer Society Press, Los Alamitos (1997)Google Scholar
  12. 12.
    Goto, S.: An Effective Algorithm for the Two-Dimensional Placement Problem in Electrical Circuit Layout. IEEE Trans. on Circuits Syst. CAS-28(1) (1981)Google Scholar
  13. 13.
    Adya, S.N., Markov, I.L.: Consistent placement of macro-block using floorplanning and standard-cell placement. In: Proc. Int. Symp. On Physical Design, pp. 12–17 (2002)Google Scholar
  14. 14.
    Hur, S.-W., Lillis, J.: Mongrel: hybrid techniques for standard cell placement. In: International Conference on Computer-Aided Design, pp. 165–170. IEEE, Los Alamitos (2000)Google Scholar
  15. 15.
    Brenner, U., Vygen, J.: Faster optimal single-row placement with fixed ordering. In: Proceedings of the conference on Design automation and test in Europe, Paris, France, March 2000, pp. 117–121 (2000)Google Scholar
  16. 16.
    Weimin, W., Xianlong, H., Yici, C., Changqi, Y., Jun, G.: A mixed mode placement algorithm for combined design of macro blocks and standard cells. In: Proceeding of ASICON 2001 (2001)Google Scholar
  17. 17.
    Viswanathan, N., Cn Chu, C.: Fastplace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model. In: ACM/IEEE International Symposium on Physical Design, Phoenix, AZ, pp. 26–33 (2004)Google Scholar
  18. 18.
    Xiu, Z., Ma, J.D., Fowler, S.M., Rutenbar, R.A.: Large-Scale Placement by Grid-Warping. In: Proc. Design Automation Conference, June 2004, pp. 351–356 (2004)Google Scholar
  19. 19.
    Eisenmann, H., Johannes, F.M.: Generic Global Placement and Floorplanning. In: Proc. of the 35th Design Automation Conference, pp. 269–274 (1998)Google Scholar
  20. 20.
    Kleinhans, J.M., Sigl, G., Johannes, F.M., Antreich, K.: Gordian: VLSI Placement by Quadratic Programming and Slicing Optimization. IEEE Trans. CAD 10(3), 356–365 (1991)Google Scholar
  21. 21.
    Sigl, G., Doll, K., Johannes, F.M.: Analytical Placement: A Linear or a Quadratic Objective Function? In: Design Automation Conf., pp. 427–432 (1991)Google Scholar
  22. 22.
    Brenner, U., Pauli, A., Vygen, J.: Almost Optimum Placement Legalization by Minimum Cost Flow and Dynamic Programming. In: Proc. ISPD 2004, pp. 2–8 (2004)Google Scholar
  23. 23.
    Doll, K., Johannes, F.M., Antreich, K.J.: Iterative placement improvement by network flow methods. Proc. IEEE Trans. CAD 13(10) (October 1994)Google Scholar
  24. 24.
    Yang, C., Hong, X., Yang, H.H., Zhou, Q., Cai, Y., Lu, Y.: Recursively Combine Floorplan and Q-Place in Mixed Mode Placement Based on Circuit’s Variety of Block Configuration. In: Proceeding of IEEE International Symposium on Circuits and Systems, vol. 5, pp. 81–84. Vancouver, Canada (2004)Google Scholar
  25. 25.

Copyright information

© Springer-Verlag Berlin Heidelberg 2005

Authors and Affiliations

  • Lijuan Luo
    • 1
  • Qiang Zhou
    • 1
  • Xianlong Hong
    • 1
  • Hanbin Zhou
    • 1
  1. 1.Dept. of Computer Science and TechnologyTsinghua Univ.BeijingChina

Personalised recommendations