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An Abstraction Algorithm for the Verification of Generalized C-Slow Designs

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Part of the Lecture Notes in Computer Science book series (LNCS,volume 1855)


A c-slow netlist N is one which may be retimed to another netlist N ’, where the number of latches along each wire of N ’ is a multiple of c. Leiserson and Saxe [1, page 54] have shown that by increasing c (a process termed slowdown) and retiming, any design may be made systolic, thereby dramatically decreasing its cycle time. In this paper we develop a new fully-automated abstraction algorithm applicable to the verification of generalized c-slow flip-flop based netlists; the more generalized topology accepted by our approach allows applicability to a fairly large class of pipelined netlists. This abstraction reduces the number of state variables and divides the diameter of the model by c; intuitively, it folds the state space of the design modulo c. We study the reachable state space of both the original and reduced netlists, and establish a c-slow bisimulation relation between the two. We demonstrate how CTL* model checking may be preserved through the abstraction for a useful fragment of CTL* formulae. Experiments with two components of IBM’s Gigahertz Processor demonstrate the effectiveness of this abstraction algorithm.


  • Induction Hypothesis
  • Model Check
  • Atomic Proposition
  • Kripke Structure
  • Reachability Analysis

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© 2000 Springer-Verlag Berlin Heidelberg

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Baumgartner, J., Tripp, A., Aziz, A., Singhal, V., Andersen, F. (2000). An Abstraction Algorithm for the Verification of Generalized C-Slow Designs. In: Emerson, E.A., Sistla, A.P. (eds) Computer Aided Verification. CAV 2000. Lecture Notes in Computer Science, vol 1855. Springer, Berlin, Heidelberg.

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67770-3

  • Online ISBN: 978-3-540-45047-4

  • eBook Packages: Springer Book Archive