Summary and Conclusions
A viable wafer-level 3D hyper-integration technology platform with dielectric adhesive bonding and copper vias has been described. An inter-wafer via-chain structure has been fabricated, demonstrating the feasibility of this 3D technology, with a baseline process flow of one-micron wafer-to-wafer alignment, BCB wafer bonding, three-step wafer thinning and copper damascene patterned inter-wafer interconnection. Evaluations indicate the thermal, mechanical, and electrical robustness of the baseline wafer bonding and thinning processes as well as compatibility with BEoL processes and packaging. The key advantages of BCB wafer bonding include the ability to accommodate wafer-level non-planarity (e.g., surface topography, wafer bow) and particulates at the bonding interfaces, high bond strength, and relatively low temperature bonding process as well as high temperature stability after bonding.
Wafer-level 3D hyper-integration offers potentially significant benefits in performance and functionality (with less material/processing constraints) over 2D ICs (including SoCs), and performance, interconnectivity, and cost benefits over die-to-wafer or die level solutions (including SiPs). Issues related to wafer alignment accuracy, thermal-mechanical stresses, thermal management, yield and common die size need to be more fully considered. However, the wafer-level 3D integration, as a future information technology, has clear advantages in performance, heterogeneous integration, and in low-cost high-volume manufacturing compared to SoCs and SiPs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
International Technology Roadmap for Semiconductors (ITRS), 2003 Edition (Semiconductor Industry Association, 2003, http://public.itrs.net/).
A. Klumpp, P. Ramm, R. Wieland, and R. Merkel, in Presentation CD of International Workshop of 3D System Integration, Fraunhofer-Institute, Munich, Germany, 2003.
Ziptronix, Inc., http://www.ziptronix.com/.
J.-Q. Lu, Y. Kwon, J.J. McMahon, A. Jindal, B. Altemus, D. Cheng et al., in Proceedings of 20th International VLSI Multilevel Interconnection Conference, T. Wade (ed.), pp. 227–236, IMIC (2003).
R.J. Gutmann, J.-Q. Lu, S. Pozder, Y. Kwon, A. Jindal, M. Celik et al., in Advanced Metallization Conference 2003 (AMC 2003), G.W. Ray, T. Smy, T. Ohta and M. Tsujimura (eds.), pp. 19–26, MRS (2004).
J.-Q. Lu, Y. Kwon, A. Jindal, K.-W. Lee, J. McMahon, G. Rajagopalan et al., in Proceedings of 19th International VLSI Multilevel Interconnection Conference, T. Wade (ed.), pp. 445–454, IMIC (2002).
K. Guarini, A. Topol, M. Ieong, R. Yu, L. Shi, D. Sing et al., in International Symposium on Thin Film Materials, Processes, and Reliability, G.S. Mathad, T.S. Cale, D. Collins, M. Engelhardt, F. Leverd, and H.S. Rathore (eds.), PV2003-13, pp. 390–404, ECS (2003).
S.J. Souri and K.C. Saraswat, in 1999 IEEE International Interconnect Technology Conference (IITC), pp. 24–26, IEEE (1999).
A. Rahman, A. Fan, J. Chung, and R. Reif, in 1999 IEEE International Interconnect Technology Conference (IITC), pp. 233–235, IEEE (1999).
P. Ramm, D. Bonfert, R. Ecke, F. Iberl, A. Klumpp, S. Riedel et al., in Advanced Metallization Conference 2001 (AMC 2001), A.J. McKerrow, Y. Shacham-Diamand, S. Zaima, and T. Ohba (eds.), pp. 159–165, MRS (2002).
K.W. Lee, T. Nakamura, T. One, Y. Yamada, T. Mizukusa, H. Hasimoto et al., in International Electron Device Meeting (IEDM) 2000, pp. 165–168, IEEE (2000).
J.A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S.J. Souri, K. Banerjee et al., Proc. IEEE, 89,3, 305–324 (2001).
K. David, in SEMI-Strategic Business Conference (SBC) 2003, Orlando, FL, April 2003.
S. List, C. Webb, S. Kim, in Advanced Metallization Conference 2002 (AMC 2002), B.M. Melnick, T.S. Cale, S. Zaima, and T. Ohta (eds.), pp. 29–36, MRS (2003).
Tezzaron Semiconductor: http://www.tezzaron.com/.
J. Burns, L. McIlrath, C. Keast, C. Lewis, A. Loomis, K. Warner et al., in 2001 IEEE International Solid-State Circuits Conference (ISSCC 2001), p. 268, IEEE (2001).
Y. Kwon, J. Seok, J.-Q. Lu, T.S. Cale and R.J. Gutmann, in Journal of The Electrochemical Society, 2004 (in press).
J.-Q. Lu, A. Jindal, Y. Kwon, J.J. McMahon, K.-W. Lee, R.P. Kraft et al., in International Symposium on Thin Film Materials, Processes, and Reliability, G.S. Mathad, T.S. Cale, D. Collins, M. Engelhardt, F. Leverd, and H.S. Rathore (eds.), PV2003-13, pp. 381–389, ECS (2003).
J.-Q. Lu, A. Jindal, Y. Kwon, J.J. McMahon, M. Rasco, R. Augur et al., in 2003 IEEE International Interconnect Technology Conference (IITC), pp. 74–76, IEEE (2003).
S. Pozder, J.-Q. Lu, Y. Kwon, S. Zollner, J. Yu, J.J. McMahon et al., in 2004 IEEE International Interconnect Technology Conference (IITC04), pp. 102–104, IEEE (2004).
Private conversation with Michelle Rasco at SEMATECH.
J. Kalyanasundharam, R.B. Iverson, E.T. Thompson, V. Prasad, T.S. Cale, R.J. Gutmann et al., in Advanced Metallization Conference 2002 (AMC 2002), B.M. Melnick, T.S. Cale, S. Zaima, and T. Ohta (eds.), pp. 59–65, MRS (2003).
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer-Verlag London Limited
About this chapter
Cite this chapter
Lu, J.Q., Cale, T.S., Gutmann, R.J. (2005). Wafer-Level Three-Dimensional Hyper-Integration Technology Using Dielectric Adhesive Wafer Bonding. In: Zschech, E., Whelan, C., Mikolajick, T. (eds) Materials for Information Technology. Engineering Materials and Processes. Springer, London. https://doi.org/10.1007/1-84628-235-7_33
Download citation
DOI: https://doi.org/10.1007/1-84628-235-7_33
Publisher Name: Springer, London
Print ISBN: 978-1-85233-941-8
Online ISBN: 978-1-84628-235-5
eBook Packages: EngineeringEngineering (R0)