Abstract
Over the last few years, the evolution of test engineering has brought it closer to design, bridging the “traditional” gap between design and test. Here, where once the design and test activities were separate and distant, the gap has been bridged by developing and adopting a unified “Design for Testability” (DfT) approach. For digital circuits and systems, DfT techniques have been embraced and are well supported. For analogue and mixed-signal circuits, the problems encountered due to the application specific nature of the circuits themselves has been a limiting factor in the widespread recognition and adoption of standardised analogue and mixed-signal DfT techniques.
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8.7 References
International Technology Roadmap for Semiconductors, 2003 Edition, “Executive Summary”
International Technology Roadmap for Semiconductors, 2003 Edition, “Test and Test Equipment”
Hurst S., “VLSI Testing digital and mixed analogue/digital techniques”, IEE, 1998, ISBN 0-85296-901-5
Rajsuman, R., “System-on-a-Chip Design and Test”, Artech House Publishers, USA, 2000, ISBN 1-58053-107-5
Rivoir J., “Lowering cost of test: parallel test or low-cost ATE?” Proceedings of the 12th Asian Test Symposium, 2003, pp360–363
Bushnell M. and Agrawal V., “Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers, 2000, ISBN 0-7923-7991-8
Needham W., “Designer’s Guide to Testable ASIC Devices”, Van Nostrand Reinhold, 1991, ISBN 0-442-00221-1
Smith M., “Application Specific Integrated Circuits”, Addison-Wesley, 1999, ISBN 0-201-50022-1
Xijiang L. et al., “High-Frequency, At-Speed Scan Testing”, IEEE Design and Test of Computers, September–October 2003, pp17–25
Zwolinski M., “Digital System Design with VHDL”, Pearson Education Limited, 2000, England, ISBN 0-201-36063-2
IEEE standard test access port and boundary-scan architecture, IEEE Std 1149.1-2001, IEEE, USA
Van treuren B. and Miranda J., “Embedded Boundary Scan”, IEEE Design and Test of Computers, March–April 2003, pp20–25
Parker K., “The Boundary-Scan Handbook, Analog and Digital”, 2nd Edition, Kluwer Academic Publishers, USA, 2000, ISBN 0-7923-8277-3
Eklow B., Barnhart C. and Parker K., “IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks”, IEEE Design and Test of Computers, September–October 2003, pp76–80
Bennetts B., “Status of IEEE testability standards 1149.4, 1532 and 1149.6”, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, 2004, Vol. 2, 2004, pp1184–1189
IEEE Std 1532-2002, IEEE Standard for In-System Configuration of Programmable Devices, IEEE, USA
Oakland S., “Considerations for implementing IEEE 1149.1 on system-on-a-chip integrated circuits”, Proceedings of the International Test Conference, 2000, pp628–637
Zorian Y., “Test requirements for embedded core-based systems and IEEE P1500”, Proceedings of the International Test Conference, 1997, pp191–199
P1500 Working Group, http://www.grouper.ieee.group/1500
Roberts G., “Metrics, Techniques and Recent Developments in Mixed-Signal Testing,” Proceedings of the IEEE/ACM International Conference on Computer Aided Design, USA, 1996, pp. 514–521
Kuijstermans, F., Sachdev, M. and Thijssen, A., “Defect-oriented test methodology for complex mixed-signal circuits”, Proceedings of the European Design and Test Conference, 1995, pp18–23
Russell G. and Learmouth D., “Systematic approaches to testing embedded analogue circuit functions”, Microelectronics Journal, No. 25, 1994, pp133–138
Dufort B. and Roberts G., “On-Chip Analog Signal Generation for Mixed-Signal Built-In Self-Test”, IEEE Journal of Solid-State Circuits, Vol. 34, No. 3, March 1999, pp318–330
Majernik, D. et al., “Using simulation to improve fault coverage of analog and mixed-signal test program sets”, Proceedings of the IEEE Autotestcon, 1997, pp371–375
Zorian Y., “Testing semiconductor chips: trends and solutions”, Proceedings of the XII Symposium on Integrated Circuits and Systems Design, 1999, pp226–233
Stoffels R., “Cost effective frequency measurement for production testing: new approaches on PLL testing”, Proceedings of the International Test Conference, 1996, pp708–716
Burbidge M. et al., “Motivations towards BIST and DfT for embedded charge-pump phase-locked loop frequency synthesisers”, IEE Proceedings on Circuits, Devices and Systems, Vol. 151, Issue 4, August 2004, pp337–348
Roberts G. and Lu A., “Analog Signal Generation for Built-In Self-Test of Mixed-Signal Integrated Circuits”, Kluwer Academic Publishers, USA, 1995, ISBN 0-7923-9564-6
Lubaszewski, M., et al., “A built-in multi-mode stimuli generator for analogue and mixed-signal testing”, Proceedings of the XI Brazilian Symposium on Integrated Circuit Design, 1998, pp175–178
Cassol L. et al., “The ΣΔ-BIST Method Applied to Analog Filters”, Journal of Electronic Testing: Theory and Applications, No. 19, 2003, pp13–20
Provost B. and Sanchez-Sinencio E., “On-Chip Ramp Generators for Mixed-Signal BIST and ADC Self-Test”, IEEE Journal of Solid-State Circuits,” Vol. 38, No. 2, February 2003, pp263–273
Guanglin W. et al., “Implementation of a BIST scheme for ADC test”, Proceedings of the 5th International Conference on ASIC, 2003, Vol. 2, 2003, pp1128–1131
de Vries R. et al., “Built-in self-test methodology for A/D converters”, Proc. of the European Design and Test Conference, 1997, pp353–358
Ohletz M., “Hybrid Built-In Self-Test (HBIST) for Mixed Analogue/Digital Integrated Circuits”, Proceedings of the European Test Conference, 1991, pp307–316
Hoffmann C. and Ohletz M., “Feasibility Study for the Hybrid-Built-In Self-Test (HBIST) for Mixed-Signal Integrated Circuits”, IEEE Design & Test of Computers, July–September 2000, pp106–115
Huertas G. et al., “Practical Oscillation-Based Test of Integrated Filters”, IEEE Design & Test of Computers, November–December 2002, pp64–72
Huertas G. et al., “Testing Mixed-Signal Cores: A Practical Oscillation-Based Test in an Analog Macro”, IEEE Design & Test of Computers, November–December 2002, pp73–82
IEEE Standard for a Mixed-Signal Test Bus, IEEE Std 1149.4-1999, IEEE, USA
Sunter S., “Cost/benefit analysis of the P1149.4 mixed-signal test bus” IEE Proceedings on Circuits, Devices and Systems, Vol. 143, No. 6, December 1996, pp393–398
Acevedo G. and Ramirez-Angulo J., “Built-in self-test scheme for on-chip diagnosis, compliant with the IEEE 1149.4 mixed-signal test bus standard”, Proceedings of the IEEE International Symposium on Circuits and Systems, Vol. 1, 2002, pp I-149–I-152
Uros K. et al., “Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test”, IEEE Design & Test of Computers, March–April 2003, pp32–39
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(2006). Design for Testability — Structured Test Approaches. In: Integrated Circuit Test Engineering. Springer, London. https://doi.org/10.1007/1-84628-173-3_8
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DOI: https://doi.org/10.1007/1-84628-173-3_8
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