Skip to main content

Digital Logic Test

  • Chapter
  • 1845 Accesses

Abstract

Digital logic forms the basis of many electronic circuits and systems from simple decoding logic through to complex microprocessor based systems. Whatever the application and complexity of the design, digital logic testing is based on a number of core principles and, provided that the design can be suitably accessed, particular test stimuli applied and the results observed, the device test problem can be addressed.

This is a preview of subscription content, log in via an institution.

Buying options

Chapter
USD   29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD   79.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD   99.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Learn about institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

3.18 References

  1. Smith M., “Application Specific Integrated Circuits”, Addison-Wesley, 1999, ISBN 0-201-50022-1

    Google Scholar 

  2. Bellaouar A. and Elmasry M., “Low-Power Digital VLSI Design Circuits and Systems”, Kluwer Academic Publishers, The Netherlands, 1995, ISBN 0-7923-9587-5

    Google Scholar 

  3. Kang S. and Leblebici Y., “CMOS Digital Integrated Circuits Analysis and Design”, McGraw-Hill International Editions, Singapore, 1996, ISBN 0-07-114423-4

    Google Scholar 

  4. International Technology Roadmap for Semiconductors (ITRS), 2003 Edition, “Design”

    Google Scholar 

  5. Zwolinski M., “Digital System Design with VHDL”, Pearson Education Limited, 2000, England, ISBN 0-201-36063-2

    Google Scholar 

  6. Smith D., “HDL Chip Design”, Doone Publications, USA, 1996, ISBN 0-9651934-3-8

    Google Scholar 

  7. Tocci R.J., Widmer N.S. and Moss G.LK., “Digital Systems 9th Edition”, Pearson Education International, USA, 2004, ISBN 0-13-121931-6

    Google Scholar 

  8. Bushnell M. and Agrawal V., “Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits”, Kluwer Academic Publishers, 2000, ISBN 0-7923-7991-8

    Google Scholar 

  9. Rajsuman, R., “System-on-a-Chip Design and Test”, Artech House Publishers, USA, 2000, ISBN 1-58053-107-5

    Google Scholar 

  10. Hurst S., “VLSI Testing digital and mixed analogue/digital techniques”, IEE, 1998, ISBN 0-85296-901-5

    Google Scholar 

  11. Needham W., “Designer’s Guide to Testable ASIC Devices”, Van Nostrand Reinhold, 1991, ISBN 0-442-00221-1

    Google Scholar 

  12. Burns M. and Roberts G.W., “An Introduction to Mixed-Signal IC Test and Measurement”, Oxford University Press, New York, 2001, ISBN 0-19-514016-8

    Google Scholar 

  13. Sabade S. and Walker D., “IDDQ Test: Will It Survive the DSM Challenge?”, IEEE D & T of Computers, Sept–Oct 2002, pp8–16

    Google Scholar 

  14. Mallarapu S. and Hoffman A., “IDDQ Testing on a Custom Automotive IC”, IEEE Journal of Solid-State Circuits, Vol. 30, No. 3, March 1995, pp295–299

    Article  Google Scholar 

  15. Champac V. Rubio A. and Figueras J., “Electrical Model of the Floating Gate Defect in CMOS ICs: Implications on IDDQ Testing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 13, No. 3, March 1994

    Google Scholar 

  16. Baker K. et al., “Development of a Class 1 QTAG Monitor”, Proceedings of the International Test Conference, 1994, pp213–222

    Google Scholar 

  17. Wallquist K., Richter A. and Hawkins C., “A General Purpose IDDQ Measurement Circuit”, Proceedings of the International Test Conference, 1993, pp642–651

    Google Scholar 

  18. Soden J.M., Hawkins C.F., Gulati R.K. and Weiwei M., “IDDQ Testing: A Review”, Journal of Electronic Testing, Theory and Applications, No. 3, 1992, pp291–303

    Google Scholar 

  19. Shen J., Maly W. and Ferguson F., “Inductive Fault Analysis of MOS Integrated Circuits”, IEEE Design and Test of Computers, Vol. 2, No. 12, December 1985, pp13–26

    Google Scholar 

  20. Jee A. and Ferguson F.J., “Carafe: An Inductive Fault Analysis Tool for CMOS VLSI Circuits”, IEEE VLSI Test Symposium, 1993, pp92–98

    Google Scholar 

  21. Ferguson F.J. and Shen J.P., “A CMOS Fault Extractor for Inductive Fault Analysis”, IEEE Transactions on Computer Aided Design, Vol, 7, No. 11, November 1988, pp1181–1194

    Google Scholar 

  22. Sachdev M. and Atzema B., “Industrial Relevance of Analog IFA: A Fact or a Fiction”, Proceedings of the International Test Conference, 1995, pp61–70

    Google Scholar 

  23. Montanes R.R., Bruls E.M. and Figueras J., “Bridging Defects Resistance Measurements in a CMOS Process”, Proceedings of the International Test Conference, 1992, pp892–899

    Google Scholar 

  24. IEEE Std 1076-2002, IEEE Standard VHDL Language Reference Manual, IEEE, USA

    Google Scholar 

  25. IEEE 1364-1995, IEEE Standard Verilog® Hardware Description Language, IEEE, USA

    Google Scholar 

  26. Datta R., Sebastine A. and Abraham J., “Delay Fault Testing and Silicon Debug Using Scan Chains”, Proceedings of the 9th IEEE European Test Symposium, May 2004, pp111–116

    Google Scholar 

  27. Garcia R., “Rethink fault models for submicron-IC test”, Test & Measurement World, October 2001

    Google Scholar 

  28. Aitken R., “Finding defects with fault models”, Proceedings of the International Test Conference, 1995, pp498–505

    Google Scholar 

  29. Bradford J. et al., “Simulating Realistic Bridging and Crosstalk Faults in an Industrial Setting”, Proceedings of the 7th IEEE European Test Symposium, 2002, pp75–80

    Google Scholar 

  30. Chess B. et al., “Logic Testing of Bridging Faults in CMOS Integrated Circuits”, IEEE Transactions on Computers, Vol. 47, No. 3, March 1998, pp338–345

    Article  Google Scholar 

Download references

Rights and permissions

Reprints and permissions

Copyright information

© 2006 Springer-Verlag London Limited

About this chapter

Cite this chapter

(2006). Digital Logic Test. In: Integrated Circuit Test Engineering. Springer, London. https://doi.org/10.1007/1-84628-173-3_3

Download citation

  • DOI: https://doi.org/10.1007/1-84628-173-3_3

  • Publisher Name: Springer, London

  • Print ISBN: 978-1-84628-023-8

  • Online ISBN: 978-1-84628-173-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics