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Information Processing with Evolutionary Algorithms pp 177–194Cite as

Evolvable Hardware Techniques for Gate-Level Synthesis of Combinational Circuits

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Part of the book series: Advanced Information and Knowledge Processing ((AI&KP))

Summary

This chapter is about the synthesis of combinational logic circuits using evolvable hardware. The chapter introduces several approaches recently followed by a number of researchers to tackle this problem. Research trends, immediate and for years to come, are presented.

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Author information

Authors and Affiliations

  1. Center Math. Research, Computer Science Section, Callejón Jalisco S/N, Guanajuato, Gto. 36240, México

    A. Hernández-Aguirre

Authors
  1. A. Hernández-Aguirre
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Editor information

Editors and Affiliations

  1. Dept. CCIA, Universidad Pais Vasco, Spain

    Manuel Graña BSc, MSc, PhD  & Alicia d’Anjou BSc, MSc, PhD  & 

  2. Grupo de Sistemas Autónomos, Universidade da Coruña, Spain

    Richard J. Duro BSc, MSc, PhD

  3. Duke University, Durham, North Carolina, USA

    Paul P. Wang PhD

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© 2005 Springer-Verlag London Limited

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Hernández-Aguirre, A. (2005). Evolvable Hardware Techniques for Gate-Level Synthesis of Combinational Circuits. In: Wu, X., Jain, L., Graña, M., Duro, R.J., d’Anjou, A., Wang, P.P. (eds) Information Processing with Evolutionary Algorithms. Advanced Information and Knowledge Processing. Springer, London. https://doi.org/10.1007/1-84628-117-2_13

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  • DOI: https://doi.org/10.1007/1-84628-117-2_13

  • Publisher Name: Springer, London

  • Print ISBN: 978-1-85233-866-4

  • Online ISBN: 978-1-84628-117-4

  • eBook Packages: Computer ScienceComputer Science (R0)

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