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Place and Route for Secure Standard Cell Design

  • Kris Tiri
  • Ingrid Verbauwhede
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 153)

Abstract

Side channel attacks can be effectively addressed at the circuit level by using dynamic differential logic styles. A key problem is to guarantee a balanced capacitive load at the differential outputs of the logic gates. The main contribution to this load is the capacitance associated with the routing between cells. This paper describes a novel design methodology to route a design in which multiple differential pairs are present. The methodology is able to route 20K+ differential routes. The differential routes are always routed in adjacent tracks and the parasitic effects between the two wires of each differential pair are balanced. The methodology is developed on top of a commercially available EDA tool. It has been developed as part of a secure digital design flow to protect security applications against Differential Power Analysis attacks. Experimental results indicate that a perfect protection is attainable with the aid of the proposed differential routing strategy.

Key words

Place & Route Differential Pair Differential Power Analysis Side Channel Attacks 

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Copyright information

© Springer Science + Business Media, Inc. 2004

Authors and Affiliations

  • Kris Tiri
    • 1
  • Ingrid Verbauwhede
    • 1
  1. 1.UC Los AngelesUSA

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