Skip to main content
SpringerLink
Log in

Low-voltage Low-power High-speed I/O Buffers

  • Chapter
Design of System on a Chip

  • 263 Accesses

Abstract

High-speed data transport is needed for today’s high-performance systems, but power consumption is a major concern, especially for portable equipment. Various popular input/output (I/O) interface schemes will be described, covering typical speed, key circuit design issues, configurations and power consumption. Among popular low-swing low-power solutions, LSI Logic’s low-voltage differential signalling (Hyper-LVDS™) buffers will be covered in more details. The list of I/O’s discussed include: HSTL, GTL/NTL, PCML, PECL, USB and matched-impedance buffers.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.00
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

6. References

  • JEDEC Standard JESD8-A (1994) Interface Standard for Nominal 3V/3.3V Supply Digital Integrated Circuits. Electron Industries Association, Virginia.

    Google Scholar 

  • JEDEC Standard JESD8-3 (1994) Gunning Transceiver Logic (GTL) Low-Level, High-Speed Interface Standard for Digital Integrated Circuits. Electron Industries Association, Virginia.

    Google Scholar 

  • EIA/JEDEC Standard EIA/JESD8-6 (1995) High Speed Transceiver Logic (HSTL) A 1.5V Output Buffer Supply Voltage Based Interface Standard for Digital Integrated Circuits. Electron Industries Association, Virginia.

    Google Scholar 

  • TIA/EIA Standard TIA/EIA-644 (1996) Electrical Characteristics of Low Voltage Differential Signaling (LVDS) Interface Circuits. Telecommunications Industry Association, Virginia.

    Google Scholar 

  • Universal Serial Bus Specification 1.0 Final Draft Revision, November 13, 1995.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. LSI Logic Corporation, 1501 McCarthy Blvd., E-186, Milpitas, CA, 95035, USA

    R. Leung

Authors
  1. R. Leung
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Universidade Federal do Rio Grande do Sul, Brasil

    Ricardo Reis

  2. Eindhoven University of Technology, The Netherlands

    Jochen A. G. Jess

Rights and permissions

Reprints and permissions

Copyright information

© 2004 Kluwer Academic Publishers

About this chapter

Cite this chapter

Leung, R. (2004). Low-voltage Low-power High-speed I/O Buffers. In: Reis, R., Jess, J.A.G. (eds) Design of System on a Chip. Springer, Boston, MA. https://doi.org/10.1007/1-4020-7929-X_8

Download citation

  • DOI: https://doi.org/10.1007/1-4020-7929-X_8

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4020-7928-3

  • Online ISBN: 978-1-4020-7929-0

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation