Skip to main content

A Brunch from the Coffee Table-Case Study in NoC Platform Design

  • Chapter
Interconnect-Centric Design for Advanced SoC and NoC

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. T. Ahonen, T. Nurmi, J. Nurmi, and J. Isoaho. Block-wise extraction of rent’s exponents for an extensible processor. In IEEE Computer Society Annual Symposium on VLSI, pages 193–199, Tampa, Florida, February 2003.

    Google Scholar 

  2. D. I. August, K. Keutzer, S. Malik, and A. R. Newton. A disciplined approach to the development of platform architectures. Microelectronics Journal, 33(11), November 2002.

    Google Scholar 

  3. H. Corporaal. Microprocessor Architectures — from VLIW to TTA. John Wiley and Sons Ltd., Chichester, West Sussex, England, 1998.

    Google Scholar 

  4. S. Deering and R. Hinden. Internet protocol, version 6 (IPv6) specification. RFC 2460, December 1998.

    Google Scholar 

  5. M. Keating and P. Bricaud. Reuse Methodology Manual for Systemon-a-Chip Designs. Kluwer Academic Publishers, Boston, second edition, June 1999. 312 pp.

    Google Scholar 

  6. J. Kylliäainen, J. Nurmi, and M. Kuulusa. COFFEE-A Core for Free. In Proceedings of the International Symposium on System-on-Chip, Tampere, Finland, November 2003.

    Google Scholar 

  7. B. S. Landman and R. L. Russo. On a pin versus block relationship for partitions of logic graphs. IEEE Transactions on Computers, C20(12):1469–1479, December 1971.

    Google Scholar 

  8. J. Lilius and D. Truscan. UML-driven TTA-based protocol processor design. In Proceedings of the 2002 Forum for Design and Specification Languages (FDL’02), Marseille, France, September 2002.

    Google Scholar 

  9. J. Lilius, D. Truscan, and S. Virtanen. Fast Evaluation of Protocol Processing Architectures for IPv6 Routing. In Proceedings of the 2003 Design, Automation and Test in Europe conference (DATE’03), Munich, Gemany, March 2003.

    Google Scholar 

  10. J. Muttersbach, T. Villiger, and W. Fichtner. Practical design of globally-asynchronous locally-synchronous systems. In Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems, Eilat, Israel, April 2000.

    Google Scholar 

  11. J. Muttersbach, T. Villiger, H. Kaeslin, N. Felber, and W. Fichtner. Globally-asynchronous locally-synchronous architectures to simplify the design of on-chip systems. In Proceedings of the 12th Annual IEEE International ASIC/SOC Conference, Washington DC, USA, September 1999.

    Google Scholar 

  12. OCP-IP Association. Open Core Protocol Specification Release 1.0. OCP-IP, 2001. www.ocpip.org.

    Google Scholar 

  13. T. Ristimäaki and J. Nurmi. Implementation of a fast 1024-bit RSA encryption on platform FPGA. In Proceedings of the 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems, Poznan, Poland, April 2003.

    Google Scholar 

  14. R. L. Rivest, A. Shamir, and L. Adleman. A method of obtaining digital signatures and public-key cryptosystems. Communications of the ACM, 21(2):120–126, 1978.

    Article  MathSciNet  Google Scholar 

  15. I. Saastamoinen, D. Sigäuenza-Tortosa, and J. Nurmi. An IP-based on-chip packet-switched network. In A. Jantsch and H. Tenhunen, editors, Networks on chip, chapter 10, pages 193–213. Kluwer Academic, 2003.

    Google Scholar 

  16. D. Tabak and G. J. Lipovski. MOVE architecture in digital controllers. IEEE Transactions on Computers, 29(2):180–190, February 1980.

    Google Scholar 

  17. S. Virtanen and J. Lilius. The TACO protocol processor simulation environment. In Proceedings of the 9th International Symposium on Hardware/Software Codesign (CODES’01), pages 201–206, Copenhagen, Denmark, April 2001.

    Google Scholar 

  18. S. Virtanen, J. Lilius, T. Nurmi, and T. Westerlund. TACO: Rapid design space exploration for protocol processors. In the Ninth IEEE/DATC Electronic Design Processes Workshop Notes, Monterey, CA, USA, April 2002.

    Google Scholar 

  19. S. Virtanen, J. Lilius, and T. Westerlund. A processor architecture for the TACO protocol processor development framework. In Proceedings of the 18th IEEE NORCHIP Conference, pages 204–211, Turku, Finland, November 2000.

    Google Scholar 

  20. S. Virtanen, D. Truscan, and J. Lilius. TACO IPv6 router — a case study in protocol processor design. Technical Report 528, Turku Centre for Computer Science, Turku, Finland, April 2003.

    Google Scholar 

  21. VSIA On-Chip Bus Development Working Group. Virtual Component Interface Standard Version 2 (OCB 2 2.0). VSI AllianceTM, April 2001. www.vsi.org.

    Google Scholar 

Download references

Author information

Authors and Affiliations

Authors

Editor information

Editors and Affiliations

Rights and permissions

Reprints and permissions

Copyright information

© 2005 Springer Science + Business Media, Inc.

About this chapter

Cite this chapter

Ahonen, T. et al. (2005). A Brunch from the Coffee Table-Case Study in NoC Platform Design. In: Nurmi, J., Tenhunen, H., Isoaho, J., Jantsch, A. (eds) Interconnect-Centric Design for Advanced SoC and NoC. Springer, Boston, MA. https://doi.org/10.1007/1-4020-7836-6_16

Download citation

  • DOI: https://doi.org/10.1007/1-4020-7836-6_16

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4020-7835-4

  • Online ISBN: 978-1-4020-7836-1

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics