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Soc Prototyping and Verification

  • Moo-Kyoung Chung
  • Young-Il Kim
  • Jae-Gon Lee
  • Wooseung Yang
  • Ando Ki
  • Chong-Min Kyung

Abstract

Verification of System-On-a-Chip (SoC) poses us a serious challenge as it involves not only high chip complexity but also hardware/software co-verification along with short design time-to-market. Traditional IC design verification technologies based on simulation, emulation, and prototyping often fall short of meeting this challenge of SoC verification. This chapter starts with an introduction of SoC design verification flow. To reduce the time-to-market it is crucial to provide the system-level model for each hardware block, software component and communication channel in the very early stage of the SoC design process. It can be best addressed by performing the so-called ‘soft prototyping.’ System-level modeling using SystemC is explained as it is expected to be widely employed as a reference model. Software part of the SoC is run on Instruction Set Simulation (ISS), which is interfaced to hardware models described in either software (like HDL or SystemC) or physical hardware. We explained the hybrid SoC design verification technique which incorporates both simulation and prototyping in a single verification environment to maximally exploit the merits of both approaches. Simulation acceleration and emulation are explained followed by the introduction of HW/SW co-simulation and FPGA-based co-emulation techniques. These techniques based on initial system-level modeling of high-level abstract behavior followed by gradual refinement and verification by comparing with the reference model, enables fast and error-free SoC design closure

Keywords

SoC Prototype Verification Soft Prototype Hard Prototype Co-Simulation Instruction Set Simulator (ISS) 

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References

  1. Accellera, 2003, Standard co-emulation modeling interface reference manual, version 1.0; http://www.eda.org/itc.Google Scholar
  2. ARM, 2002, ARM System-Level Modeling; http://www.arm.com.Google Scholar
  3. ARM, 2003, AMBA AHB Cycle Level Interface (AHB CLI) Specification; http://www.arm.com.Google Scholar
  4. ARM, 2004, ARM RealView Versatile Family Flyer; http://www.arm.com.Google Scholar
  5. ARM, 2005, ARM RealView Integrator Family Flyer; http://www.arm.com.Google Scholar
  6. Bammi, J. R., Harcourt, E., Kruijtzer, W., Lavagno, L. and Lazarescu, M. T., 2000, Software performance estimation strategies in a system-level design tool, Proceedings of International Workshop on Hardware/Software Codesign, pp. 82-86.Google Scholar
  7. Bauer, M., Echer, E., Henftling, R., and Zinn, A., 1999, A method for accelerating test environments, EUROMICRO Conference.Google Scholar
  8. Bauer, J., Bershteyn, M., Kaplan, I., and Vyedin, P., 1998, A reconfigurable logic machine for fast event-driven simulation, Design Automation Conference (DAC).Google Scholar
  9. Benini, L., Bertozzi, D., Bruni, D., Drago, N., Fummi, F. and Poncino, M., 2003, SystemC cosimulation and emulation of multiprocessor SoC designs, IEEE Computer, 36(4):53-59Google Scholar
  10. Blaurock, O., 2004, A systemc-based modular design and verification framework for C-model reuse in a HW/SW-codesign flow, Proceedings of International Conference on Distributed Computing Systems Workshops, pp. 838-843.Google Scholar
  11. Cai, L. and Gajski, D., 2003, Transaction Level Modeling: An Overview. In Proc. IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS’03), Newport Beach CA USA, pp. 19-24.Google Scholar
  12. Caldari, M., Conti, M., Coppolar, M., Curaba, S., Pieralisi, L., and Turchetti, 2003, Transaction-level models for AMBA bus architecture using SystemC 2.0, In Proc. Design, Automation and Test in Europe and Exhibition (DATE’03), Munich Germany, pp. 26-31.Google Scholar
  13. Chang, H., Cooke, L., Hunt, M., Martin, G., McNelly, A., and Todd, L., 1999, Surviving SOC Revolution: A Guide To Platform-Based Design, Kluwer Academic Publishers.Google Scholar
  14. Chung, M. K. and Kyung, C. M., 2004, Improvement of compiled instruction set simulator by increasing flexibility and reducing compile time, Proceedings of International Workshop on Rapid System Prototyping, pp. 38-44.Google Scholar
  15. Chung, M. K., Yang, S., Lee, S. H. and Kyung, C. M., 2005, System-level HW/SW co-simulation framework for multiprocessor and multithread SoC, Proceedings of International Symposium on VLSI Design, Automation and Test, IEEE, pp. 177-180.Google Scholar
  16. Clouard, A., 2002, Experiences and Challenges of Transaction-Level Modeling with SystemC 2.0, ST Microelectronics, presentation at the 5th European SystemC User Group Meeting.Google Scholar
  17. Clouard, A. Jain, K., Ghensassia, F., Maillet-Contoz, L., Strassen, J.-P., 2003, SystemC: Methodology and Applications, Muller, W., Rosenstiel, W., and Ruf, J., ed., Kluwer Academic Publishers.Google Scholar
  18. Cmelik, B. and Keppel, D., 1994, Shade: a fast instruction-set simulator for execution profiling, Proceedings of International Conference on Measurement and Modeling of Computer Systems, ACM SIGMETRICS, pp. 128-137.Google Scholar
  19. Dynalith Systems, 2000, iSAVE User Manual, ttp://www.dynalith.com.Google Scholar
  20. Dynalith Systems, 2002, iPROVE User Manual, http://www.dynalith.com.Google Scholar
  21. Dynalith Systems, 2003, iPROVE SCE-MI Coemulation Manual, http://www.dynalith.com.Google Scholar
  22. Dynalith Systems, 2004a, PhysicalModler, http://www.dynalith.com.Google Scholar
  23. Dynalith Systems, 2004b, iPROVE AMBA Package Manual, http://www.dynalith.com.Google Scholar
  24. Eiriksson, A.T., 1990, Mixed-level simulation with a Zycad simulation engine, ASIC Seminar and Exhibit, 1990. pp. P5/1.1-P5/1.5.Google Scholar
  25. Gharsalli, F.; Meftali, S.; Rousseau, F.; Jerraya, A.A., 2002, Automatic generation of embedded memory wrapper for multiprocessor SoC, Design Automation Conference, pp. 596-601.Google Scholar
  26. Grotker, T., Liao, S., Martin, G., and Swan, S., 2002, Chapter 8 Transaction-level modeling, in: System Design with SystemC. Kluwer Academic Publishers.Google Scholar
  27. Keating, M. and Bricaud, P., 1999, Reuse Methodology Manual for System-On-a-Chip Designs, 2nd ed., Kluwer Academic Publishers, pp. 224-247.Google Scholar
  28. Ki, A., Park, B.I., Lee, J.G., and Kyung, C.M., 2003, Cycle-accurate co-emulation with SystemC, SoC Design Conference, COEX ASEM Hall, Seoul Korea.Google Scholar
  29. Ki, A. and Kim, Y.I., 2005, Reducing lock-step overhead of hardware-assisted simulation acceleration using protocol awareness, International SoC Conference, Seoul Korea.Google Scholar
  30. Kim, N., Choi, H., Lee, S., Park, I.-C. And Kyung C.M., 1998, Virtual Chip:Making Functional Models Work on Real Target Systems, Design Automation Conference (DAC), pp.170-173.Google Scholar
  31. Kim, Y.I., Yang, W., Kwon, Y.S., and Kyung, C.M., 2004, Communication-efficient hardware acceleration for fast functional simulation, Design Automation Conference (DAC), pp. 293-298.Google Scholar
  32. Lee, J. Y. and Park, I. C., 2003, Timed compiled-code functional simulation of embedded software for performance analysis of SOC design, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 22(1):1-14CrossRefGoogle Scholar
  33. Nohl, A., Braun, G., Schliebusch, O., Leupers, R., Meyr, H. and Hoffmann A., 2002, A universal technique for fast and flexible instruction-set architecture simulation, Proceedings of Design Automation Conference, pp. 22-27.Google Scholar
  34. OSCI, 2005, Draft Standard SystemC Language Reference Manual, http://www.systemc.org.Google Scholar
  35. Pasricha, S., 2002, Transaction level modeling of SoC with SystemC 2.0, In Synopsys Users Group Conference India (SNUG’02), India.Google Scholar
  36. Pees, S., Hoffmann, A., Zivojnovic, V. and Meyr, H., 1999, LISA-machine description language for cycle-accurate models of programmable DSP architectures, Proceedings of Design Automation Conference, pp. 933-938.Google Scholar
  37. Rashinkar, P., Paterson, P., and Singh, L., 2001, 5.8 Simulation acceleration, in: System-on-a-chip Verification: Methodology and Techniques, 1st ed., Kluwer Academic Publishers, pp. 223-234.Google Scholar
  38. Rosenstiel W., 2000, Chapter 3 Prototyping and emulation, in: Hardware/Software Co-Design: Principles and Practice, Staunstrup, J. and Wolf, W., ed., 1st ed., Kluwer Academic Publishers, pp. 75-78.Google Scholar
  39. Schnarr, E. C., Hill, M. D. and Larus, J. R., 2001, Facile: a language and compiler for high-performance processor simulators, Proceedings of Programming Language Design and Implementation, ACM SIGPLAN, pp. 321-331.Google Scholar
  40. Synopsys, 2003a, CoCentric System Studio User Guide, Version U-2003.03; http://www.synopsys.com.Google Scholar
  41. Synopsys, 2003b, DesignWare AMBA SystemC Library User Guide; http://www.synopsys.com.Google Scholar
  42. Synopsys, 2003c, DesignWare ARM SystemC Library User Guide; http://www.synopsys.com.Google Scholar
  43. Wieferink, A., Kogel, T., Leupers, R., Ascheid, G., and Meyr, H., 2004, A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms. In Proc. Design, Automation and Test in Europe and Exhibition (DATE’04), Paris France, pp. 1256-1261.Google Scholar
  44. Witchel, E. and Rosenblum, M., 1996, Embra: fast and flexible machine simulation, Proceedings of International Conference on Measurement and Modeling of Computer Systems, ACM SIGMETRICS, pp. 68-79.Google Scholar
  45. Zhu, J. and Gajski, D. D., 2002, An ultra-fast instruction set simulator, IEEE Transactions on Very Large Scale Integration Systems, 10(3): 363-373.CrossRefGoogle Scholar
  46. Zivojnovic, V., Tjiang, S. and Meyr, H., 1995, Compiled simulation of programmable DSP architectures, Proceedings of Workshop on VLSI Signal Processing, IEEE, pp. 187-196.Google Scholar

Copyright information

© Springer 2006

Authors and Affiliations

  • Moo-Kyoung Chung
    • 1
  • Young-Il Kim
    • 2
  • Jae-Gon Lee
    • 1
  • Wooseung Yang
    • 2
  • Ando Ki
    • 2
  • Chong-Min Kyung
    • 1
  1. 1.Korea Advanced Institute of Science and TechnologyKorea
  2. 2.Dynalith Systems Co., Ltd.Korea

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