Abstract
This paper describes a new RFIC design flow methodology and is based upon the RFIC Reference Flow recently jointly developed by Cadence, Agilent and Helic. The flow described addresses many of the problems associated with the performance verification of RFIC circuit blocks developed for wireless systems applications. The flow is based upon the Cadence® Virtuoso® custom design platform and utilises simulation engines and additional capability provided in Agilent Technologies RF Design Environment (RFDE).
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© 2006 Springer
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Morris, D., EDA, A.E. (2006). A NEW METHODOLOGY FOR SYSTEM VERIFICATION OF RFIC CIRCUIT BLOCKS. In: Steyaert, M., Huijsing, J., van Roermund, A. (eds) Analog Circuit Design. Springer, Dordrecht. https://doi.org/10.1007/1-4020-3885-2_9
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DOI: https://doi.org/10.1007/1-4020-3885-2_9
Publisher Name: Springer, Dordrecht
Print ISBN: 978-1-4020-3884-6
Online ISBN: 978-1-4020-3885-3
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