Abstract
Reconfigurable computing experienced a considerable expansion in the last few years, due in part to the fast run-time partial reconfiguration features offered by recent SRAM-based Field Programmable Gate Arrays (FPGAs), which allowed the implementation in real-time of dynamic resource allocation strategies, with multiple independent functions from different applications sharing the same logic resources in the space and temporal domains.
However, when the sequence of reconfigurations to be performed is not predictable, the efficient management of the logic space available becomes the greatest challenge posed to these systems. Resource allocation decisions have to be made concurrently with system operation, taking into account function priorities and optimizing the space currently available. As a consequence of the unpredictability of this allocation procedure, the logic space becomes fragmented, with many small areas of free resources failing to satisfy most requests and so remaining unused.
A rearrangement of the currently running functions is therefore necessary, so as to obtain enough contiguous space to implement incoming functions, avoiding the spreading of their components and the resulting degradation of system performance. A novel active relocation procedure for Configurable Logic Blocks (CLBs) is herein presented, able to carry out online rearrangements, defragmenting the available FPGA resources without disturbing functions currently running.
This work was supported by Fundação para a Ciência e Tecnologia under contract number POCTI/33842/ESE/2000
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Cantó, E., J. M. Moreno, J. Cabestany, I. Lacadena, and J. M. Insenser. (2001). “A Temporal Bipartitioning Algorithm for Dynamically Reconfigurable FPGAs,” IEEE Trans. on VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 210–218.
Cardoso, J. M. P., and H. C. Neto. (1999). “An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs,” Proc. 10th Intl. Conf. on VLSI, pp. 485–496.
Compton, K., Z. Li, J. Cooley, S. Knol, and S. Hauck. (2002). “Configuration, Relocation and Defragmentation for Run-Time Reconfigurable Computing,” IEEE Trans. on VLSI Systems, Vol. 10, No. 3, June 2002, pp. 209–220.
Diessel, O., H. El Gindy, M. Middendorf, H. Schmeck, and B. Schmidt. (2000). “Dynamic scheduling of tasks on partially reconfigurable FPGAs,” IEE Proc.-Computer Digital Technology, Vol. 147, No. 3, May 2000, pp. 181–188.
Gericota, M. G., G. R. Alves, M. L. Silva, and J. M. Ferreira. (2002). “On-line Defragmentation for Run-Time Partially Reconfigurable FPGAs.” In Glesner, M., Zipf, P., and Renovell, M., editors, Proc. 12th Intl. Conf. Field Programmable Logic and Applications: Reconfigurable Computing is Going Mainstream, Lecture Notes in Computer Science 2438, pp. 302–311. Springer.
Gericota, M. G., G. R. Alves, M. L. Silva, and J. M. Ferreira. (2003). “Run-Time Management of Logic Resources on Reconfigurable Systems,” Proc. Design, Automation and Test in Europe, pp. 974–979.
Hauck, S., and G. Borriello. (1997). “An Evaluation of Bipartitioning Techniques,” IEEE Trans. on Computer Aided Design of Integrated Circuits and Systems, Vol. 16, No. 8, Aug. 1997, pp. 849–866.
Huang, W., and E. J. McCluskey. (2001). “A Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations,” Proc. 9th ACM Intl. Symp. Field Programmable Gate Arrays, pp. 183–192.
Jeong, B., S. Yoo, S. Lee, and K. Choi. (2000). “Hardware-Software Cosynthesis for Run-time Incrementally Reconfigurable FPGAs,” Proc. 2000 Asia South Pacific Design Automation Conf., pp. 169–174.
Kaul, M., and R. Vemuri. (1999). “Temporal Partitioning Combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs,” Proc. Design, Automation and Test in Europe, pp. 202–209.
Li, Z., and S. Hauck. (2002). “Configuration Prefetching Techniques for Partial Reconfigurable Coprocessor with Relocation and Defragmentation,” Proc. 10th ACM Int. Symp. Field-Programmable Gate Arrays, pp. 187–195.
Long, X. P., and H. Amano. (1993). “WASMII: a Data Driven Computer on a Virtual Hardware,” Proc. 1st IEEE Workshop on FPGAs for Custom Computing Machines, pp. 33–42.
Maestre, R., F. J. Kurdahi, R. Hermida, N. Bagherzadeh, and H. Singh. (2001). “A Formal Approach to Context Scheduling for Multicontext Reconfigurable Architectures,” IEEE Trans. on VLSI Systems, Vol. 9, No. 1, Feb. 2001, pp. 173–185.
Meißner, M., S. Grimm, W. Straßer, J. Packer, and D. Latimer. (2001). “Parallel Volume Rendering on a Single-Chip SIMD Architecture,” Proc. IEEE Symp. on Parallel and Large-data Visualization and Graphics, pp. 107–113.
Sanchez-Elez, M., M. Fernandez, R. Maestre, R. Hermida, N. Bagherzadeh, and F. J. Kurdahi. (2002). “A Complete Data Scheduler for Multi-Context Reconfigurable Architectures,” Proc. Design, Automation and Test in Europe, pp. 547–552.
Singh, H., M.-H. Lee, G. Lu, F. J. Kurdahi, N. Bagherzadeh, and E. M. C. Filho. (2000). “MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications,” IEEE Trans. on Computers, Vol. 49, No. 5, May 2000, pp. 465–481.
Teich, M., S. Fekete, and J. Schepers. (1999). “Compile-time optimization of dynamic hardware reconfigurations,” Proc. Intl. Conf. on Parallel and Distributed Processing Techniques and Applications, pp. 1097–1103.
Trimberger, S. (1998). “Scheduling designs into a time-multiplexed FPGA,” Proc. Int. Symp. Field Programmable Gate Arrays, pp. 153–160.
Vasilko, M. (1999). “DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems,” Proc. 9th Intl.Workshop on Field-Programmable Logic and Applications, pp. 124–133.
“The Programmable Logic Data Book,” Xilinx, Inc., 2002.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2005 Springer
About this chapter
Cite this chapter
Gericota, M.G., Alves, G.R., Silva, M.L., Ferreira, J.M. (2005). Run-time Defragmentation for Dynamically Reconfigurable Hardware. In: Lysaght, P., Rosenstiel, W. (eds) New Algorithms, Architectures and Applications for Reconfigurable Computing. Springer, Boston, MA. https://doi.org/10.1007/1-4020-3128-9_10
Download citation
DOI: https://doi.org/10.1007/1-4020-3128-9_10
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4020-3127-4
Online ISBN: 978-1-4020-3128-1
eBook Packages: EngineeringEngineering (R0)