1.3 Summary
SystemVerilog unifies several proven hardware design and verification languages, in the form of extensions to the Verilog HDL. These extensions provide powerful new capabilities for modeling hardware at the RTL, system and architectural levels, along with a rich set of features for verifying model functionality.
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© 2006 Springer Science+Business Media, LLC
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(2006). Introduction to SystemVerilog. In: SystemVerilog for Design. Springer, Boston, MA. https://doi.org/10.1007/0-387-36495-1_1
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DOI: https://doi.org/10.1007/0-387-36495-1_1
Publisher Name: Springer, Boston, MA
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