HDI Substrate Manufacturing Technologies: Thin Film Technology

Keywords

Conductor Metal Print Wiring Board Thin Film Technology Mask Aligner Multichip Module 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    Richard Brown, “RF/Microwave Hybrids: Basics, Materials and Processes”, Kluwer Academic Publishers, New York, NY (2003). Google Scholar
  2. [2]
    A. Elasabini-Riad and F.D. Barlow III, “Thin Film Technology Handbook”, Chapter 3, McGraw Hill, New York, NY (2003). Google Scholar
  3. [3]
    M. Pecht, et al.“Integrated Circuit, Hybrid, and Multichip module Packaging Design Guidelines”, Wiley InterScience, New York, NY (1992). Google Scholar
  4. [4]
    James J. Licari and Leonard R. Enlow, “Hybrid Microcircuit Technology Handbook”, Noyes Publications, (1998). Google Scholar
  5. [5]
    T. Gupta, “Handbook of Thick film and Thin Film Hybrid Microelectronics”, Kluwer Academic Publishing, New York, NY (2003). CrossRefGoogle Scholar
  6. [6]
    R. Forman, “Photoresist Options for Wafer-Level Packaging”, Chip Scale Review, August (2003). Google Scholar
  7. [7]
    R. Forman, “Electrodeposited Photo Resist for Wafer Applications”, 5 th Annual SECAP East Asia Seminar Series, Nov. (2004). Google Scholar
  8. [8]
    D. Tonnies, “How to Select the ‘Right’ Photolithography Tool for Wafer Bumping and Wafer-Level Packaging”, Chip Scale Review, July (2005). Google Scholar
  9. [9]
    R. Pelzer, et al., “Lithography for Wafer-Level Packaging”, Chip Scale Review, July (2004). Google Scholar
  10. [10]
    D. Tonnies, “Mask Aligners for IC Packaging Applications”, Chip Scale Review, July (2004). Google Scholar
  11. [11]
    E.D. Perfecto, et al., “Thin-Film Multichip Module Packages for High-End IBM Servers”, IBM Journal of Research and Development, Vol. 42, Number 5 (1998). Google Scholar
  12. [12]
    E. Beyne and E. Parton, “A Novel MCM Technology”, Advanced Packaging, October (2002). Google Scholar
  13. [13]
    K. Wong, et al., “Metallization by Plating for High-performance Multichip Modules”, IBM Journal of Research and Development, Vol. 42, Number 5 (1998). Google Scholar
  14. [14]
    S. Krongelb, et al., “Electrochemical Process for Advanced Package Fabrication”, IBM Journal of Research and Development, Vol. 42, Number 5 (1998). Google Scholar
  15. [15]
    J. Gregus, et al., “Chip-Scale Modules for High-Level Integration in the 21st Century”, Bell Labs Technical Journal, July-September (1998). Google Scholar
  16. [16]
    R. Frye, et al., “Silicon-on-Silicon MCMs with Integrated Passive Components”, Proc. MCM Conference, March (1992). Google Scholar
  17. [17]
    C. Neugebauer, et al., “High Performance Interconnection Between VLSI Chips”, Solid State Technology, June (1988). Google Scholar
  18. [18]
    R. Fillion, et al., “Advance 3-D Stacked Technology,” Electronics Packaging Technology Conference, Singapore, Conf. Proc., pp. 13–18, Dec. 10, 2003. Google Scholar
  19. [19]
    Intel, “Bumpless Build Up Layer Packaging”, available at http://www.intel.com/technology/silicon/packaging.htm.
  20. [20]
    “CII iNEMI 2004 Technology Roadmap”, available at www.imaps.org/cii/cii_roadmap_2004.pdf.

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© Springer Science+Business Media LLC 2007

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