Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems

  • Jürgen Becker
  • Michael Hübner
  • Michael Ullmann
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 200)

Abstract

The paper describes a new approach of a flexible run-time system for handling dynamic function reconfiguration in fine-grain Virtex FPGAs, whereas the fulfillment of given real-time constraints are central. Moreover, the detailed evaluation and measurement of the power consumption situation during this dynamic reconfiguration process is essential for realistically quantifying the power loss of fine-grain FPGAs during dynamic reconfiguration processes. This kind of real-time run-time systems and power analysis give the designer and user the possibility to compare FPGA implementation alternatives and to apply the required functionality reconfigurations during the selected application scenarios. Thus, a qualified decision can be done between fine-grain FPGAs of different sizes and different dynamic reconfiguration frequencies, e.g. using smaller and more cost- as well as power-efficient FPGAs by temporarily outsourcing suitable functionalities.

Key words

Virtex FPGA power consumption real-time run-time reconfiguration function and data management 

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Copyright information

© International Federation for Information Processing 2006

Authors and Affiliations

  • Jürgen Becker
    • 1
  • Michael Hübner
    • 1
  • Michael Ullmann
    • 1
  1. 1.Institut für Technik der Informationsverarbeitung (ITIV)Universität Karlsruhe (TH)Germany

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