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On-Chip Property Verification Using Assertion Processors

  • José Augusto M. Nacif
  • Claudionor Nunes CoelhoJr.
  • Harry Foster
  • Flávio Miana de Paula
  • Edjard Mota
  • Márcia Roberta Falcão Mota
  • Antônio Otávio Fernandes
Part of the IFIP International Federation for Information Processing book series (IFIPAICT, volume 200)

Abstract

White-box verification is a technique that reduces observability problems by locating a failure during design simulation without the need to propagate the failure to the I/O pins. White-box verification in chip level designs can be implemented using assertion checkers to ensure the correct behavior of a design. With chip gate counts growing exponentially, today’s verification techniques, such as white-box, can not always ensure a bug free design. This paper proposes an assertion processor to be used with synthesized assertion checkers in released products to enable intelligent debugging of deployed designs. Extending white-box verification techniques to deployed products helps locate errors that were not found during simulation / emulation phases. We present results of the insertion of assertion checkers and an assertion processor in an 8-Bit processor and a communication core.

Keywords

On-line verification assertion processor assertion-based verification 

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Copyright information

© International Federation for Information Processing 2006

Authors and Affiliations

  • José Augusto M. Nacif
    • 1
  • Claudionor Nunes CoelhoJr.
    • 1
  • Harry Foster
    • 2
  • Flávio Miana de Paula
    • 3
  • Edjard Mota
    • 4
  • Márcia Roberta Falcão Mota
    • 5
  • Antônio Otávio Fernandes
    • 1
  1. 1.Computer Science DepartmentUniversidade Federal de Minas Gerais, MGBrazil
  2. 2.Jasper Design AutomationMountain ViewUSA
  3. 3.MindSpeed TechnologiesNewport BeachUSA
  4. 4.INDT - Instituto Nokia de Tecnologia, AMBrazil
  5. 5.Computer Science DepartmentUniversidade Federal do Amazonas, AMBrazil

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